CPRI Intel® FPGA IP User Guide

ID 683595
Date 4/04/2022
Public

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3.15.2.4. Writing the Hyperframe Control Words

A control transmit table contains one entry for each of the 256 control words in the current hyperframe. Each control transmit table entry contains a control word and an enable bit. As the frame is created, if a control word entry is enabled, and the global tx_ctrl_insert_en bit in the L1_CONFIG register is set, the IP core writes the appropriate control transmit table entry to the CPRI frame's control word.

Control Word Writing Example when Data path width is set to 32:

You write to a control transmit table entry through the TX_CTRL register. This register access method requires that you write the control word in 32-bit sections. Use the tx_ctrl_seq field of the CTRL_INDEX register to specify the 32-bit section you are currently writing to the TX_CTRL register.

To write a control word in the control transmit table, perform the following steps after frame synchronization (state_l1_synch is 3’h6) is achieved. When you write to a specific field of a register, do not clear other bits.

  1. Write the control word number X to the tx_ctrl_x field of the CTRL_INDEX register.
  2. Reset the tx_ctrl_seq field of the CTRL_INDEX register to the value of zero.
  3. Write the first 32-bit section of the next intended #Z.X control word to the TX_CTRL register.
  4. Set the tx_ctrl_insert bit of the CTRL_INDEX register to the value of 1.
  5. If the CPRI line bit rate is greater than 2.4576 Gbps, increment the tx_ctrl_seq field of the CTRL_INDEX register to the value of 1 and write the second 32-bit section of the next intended #Z.X control word to the TX_CTRL register.
  6. Set the tx_ctrl_insert bit of the CTRL_INDEX register to the value of 1.
  7. If the CPRI line bit rate is greater than 4.9152 Gbps, increment the tx_ctrl_seq field of the CTRL_INDEX register to the value of 2 and write the third 32-bit section of the next intended #Z.X control word to the TX_CTRL register.
  8. Set the tx_ctrl_insert bit of the CTRL_INDEX register to the value of 1.
  9. If the CPRI line bit rate is greater than 6.144 Gbps, increment the tx_ctrl_seq field of the CTRL_INDEX register to the value of 3 and write the fourth 32-bit section of the next intended #Z.X control word to the TX_CTRL register.
  10. Set the tx_ctrl_insert bit of the CTRL_INDEX register to the value of 1.
  11. If the CPRI line bit rate is 10.1376 Gbps, increment the tx_ctrl_seq field of the CTRL_INDEX register to the value of 4 and write the fifth 32-bit section of the next intended #Z.X control word (the real-time vendor specific bytes) to the TX_CTRL register.
  12. Set the tx_ctrl_insert bit of the CTRL_INDEX register to the value of 1.
  13. After you update the control transmit table, set the tx_ctrl_insert_en bit of the L1_CONFIG register to enable the CPRI IP core to write the values from the control transmit table to the control words in the outgoing CPRI frame.

Control Word Writing Example when Data path width is set to 64:

To write a control word in the control transmit table, perform the following steps after frame synchronization (state_l1_synch is 3’h6) is achieved. When you write to a specific field of a register, do not clear other bits.

  1. Write the control word number X to the tx_ctrl_x field of the CTRL_INDEX register.
  2. Reset the tx_ctrl_seq field of the CTRL_INDEX register to the value of zero.
  3. Write the first 32-bit section of the next intended #Z.X control word to the TX_CTRL register.
  4. Set the tx_ctrl_insert bit of the CTRL_INDEX register to the value of 1.
  5. If the CPRI line bit rate is greater than 2.4576 Gbps, increment the tx_ctrl_wpos field of the CTRL_INDEX register to the value of 1 and read the second 32-bit section of the next intended #Z.X control word to the TX_CTRL register.
  6. Set the tx_ctrl_insert bit of the CTRL_INDEX register to the value of 1.
  7. If the CPRI line bit rate is greater than 4.9152 Gbps, increment the tx_ctrl_seq and clear the rx_ctrl_wpos fields of the CTRL_INDEX register to the value of 1 and 0 respectively and read the 32-bit section of the next intended #Z.X control word to the TX_CTRL register.
  8. Set the tx_ctrl_insert bit of the CTRL_INDEX register to the value of 1.
  9. If the CPRI line bit rate is greater than 6.144 Gbps, increment the tx_ctrl_wpos field of the CTRL_INDEX register to the value of 1 and read the fourth 32-bit section of the next intended #Z.X control word to the RX_CTRL register.
  10. Set the tx_ctrl_insert bit of the CTRL_INDEX register to the value of 1.
  11. If the CPRI line bit rate is greater than 9.8304 Gbps, increment the tx_ctrl_seq and clear the tx_ctrl_wpos field of the CTRL_INDEX register to the value of 2 and 0 respectively and write the fifth 32-bit section of the next intended #Z.X control word to the TX_CTRL register.
  12. Set the tx_ctrl_insert bit of the CTRL_INDEX register to the value of 1.
  13. If the CPRI line bit rate is 10.1376 Gbps, increment the tx_ctrl_wpos field of the CTRL_INDEX register to the value of 1 and write the sixth 32-bit section of the next intended #Z.X control word (the real-time vendor specific bytes) to the TX_CTRL register.
  14. Set the tx_ctrl_insert bit of the CTRL_INDEX register to the value of 1.
  15. If the CPRI line bit rate is 24.33024 Gbps, increment the tx_ctrl_seq/tx_ctrl_wpos in a similar pattern to transmit subsequent 32-bit section to the TX_CTRL register.

The tx_control_insert bit of the CTRL_INDEX register enables or disables the transmission of the corresponding control transmit table entry in the CPRI frame. The tx_ctrl_insert_en bit of the L1_CONFIG register is the master enable: when it is set, the CPRI IP core writes all table entries with the tx_ctrl_insert bit set into the CPRI frame.

Control Word Transmission Example

To write the vendor-specific portion of the control word in a transmitted hyperframe, perform the following steps:

  1. Identify the indices for the vendor-specific portion of the transmit control table, using the formula X = Ns + 64 * Xs.

    In the example, Ns = 16 and Xs = 0, 1, 2, and 3. Therefore, the indices to be read are 16, 80, 144, and 208.

  2. For each value X in 16, 80, 144, and 208, perform the sequence of steps listed above.

    After you update the control transmit table with the control bytes, to insert the data in the next outgoing CPRI frame, make sure that you set thetx_ctrl_insert_en bit of the L1_CONFIG register to the value of 1 as specified in the instructions.

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