CPRI Intel® FPGA IP User Guide

ID 683595
Date 4/04/2022
Public

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4.2. CPRI Intel® FPGA IP Core L1 Direct Access Interfaces

The CPRI IP can communicate with the surrounding design through multiple optional interfaces that provide direct access to all or part of the CPRI frame.

Table 50.  L1 Direct Access Interface SignalsThe Data path width parameter determines the interface type and width, where N= 32 or 64, C= 3 or 7, and D= 31 or 63.

Signal Name

Direction

Description

auxN_rx_ctrl[C:0] Output AUX RX interface status signals

These signals are available only if you turn on Enable auxiliary interface in the CPRI parameter editor.

auxN_rx_rfp Output
auxN_rx_hfp Output
auxN_rx_bfn[11:0] Output
auxN_rx_z[7:0] Output
auxN_rx_x[7:0] Output
auxN_rx_seq[6:0] Output
auxN_rx_data[D:0] Output AUX RX interface data signals

These signals are available only if you turn on Enable auxiliary interface in the CPRI parameter editor.

auxN_rx_ctrl[C:0] Output
auxN_tx_sync_rfp Input AUX TX interface control and status signals

These signals are available only if you turn on Enable auxiliary interface in the CPRI parameter editor.

auxN_tx_error Output
auxN_tx_ctrl[C:0] Output
auxN_tx_err[C:0] Output
auxN_tx_rfp Output
auxN_tx_hfp Output
auxN_tx_bfn[11:0] Output
auxN_tx_z[7:0] Output
auxN_tx_x[7:0] Output
auxN_tx_seq[6:0] Output
auxN_tx_data[D:0] Input AUX TX interface data signals

These signals are available only if you turn on Enable auxiliary interface in the CPRI parameter editor.

auxN_tx_mask[D:0] Input
auxN_tx_ctrl[C:0] Output
iqN_rx_valid[C:0] Output Direct IQ RX interface

These signals are available only if you turn on Enable direct IQ mapping interface in the CPRI parameter editor.

iqN_rx_data[D:0] Output
iqN_tx_ready[C:0] Output Direct IQ TX interface

These signals are available only if you turn on Enable direct IQ mapping interface in the CPRI parameter editor.

iqN_tx_valid[C:0] Input
iqN_tx_data[D:0] Input
ctrlN_axc_rx_valid[C:0] Output Direct Ctrl_AxC RX interface

These signals are available only if you turn on Enable direct ctrl_axc access interface in the CPRI parameter editor.

ctrlN_axc_rx_data[D:0] Output
ctrlN_axc_tx_ready[C:0] Output Direct Ctrl_AxC TX interface

These signals are available only if you turn on Enable direct ctrl_axc access interface in the CPRI parameter editor.

ctrl_axc_tx_valid[3:0] Input
ctrlN_axc_tx_data[D:0] Input
vsN_rx_valid[C:0] Output Direct VS RX interface

These signals are available only if you turn on Enable direct vendor specific access interface in the CPRI parameter editor.

vsN_rx_data[D:0] Output
vsN_tx_ready[C:0] Output Direct VS TX interface

These signals are available only if you turn on Enable direct vendor specific access interface in the CPRI parameter editor.

vsN_tx_valid[C:0] Input
vsN_tx_data[D:0] Input
rtvsN_rx_valid Output Direct RTVS RX interface

These signals are available only if you turn on Enable direct real-time vendor specific interface in the CPRI parameter editor.

rtvsN_rx_data[D:0] Output
rtvsN_tx_ready Output Direct RTVS TX interface

These signals are available only if you turn on Enable direct real-time vendor specific interface in the CPRI parameter editor.

rtvsN_tx_valid Input
rtvsN_tx_data[D:0] Input
hdlc_rx_valid Output Direct HDLC serial RX interface

These signals are available only if you turn on Enable HDLC serial interface in the CPRI parameter editor.

hdlc_rx_data Output
hdlc_tx_ready Output Direct HDLC serial TX interface

These signals are available only if you turn on Enable HDLC serial interface in the CPRI parameter editor.

hdlc_tx_valid Input
hdlc_tx_data Input
z130_local_lof Output Direct L1 control and status interface

These signals are available only if you turn on Enable direct Z.130.0 alarm bits access interface in the CPRI parameter editor.

z130_local_los Output
z130_sdi_assert Input
z130_local_rai Output
z130_reset_assert Input
z130_remote_lof Output
z130_remote_los Output
z130_sdi_req Output
z130_remote_rai Output
z130_reset_req Output

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