Visible to Intel only — GUID: nik1411442204119
Ixiasoft
Visible to Intel only — GUID: nik1411442204119
Ixiasoft
5.13. CTRL_INDEX Register
Bits | Field Name | Type | Value on Reset | Description |
---|---|---|---|---|
31:28 | Reserved | UR0 | 5'b0 | — |
27 | rx_ctrl_wpos | RW | 1'b0 | This field is only available when you set the parameter Data path width value to 64. The value in this field determines the 32-bit section in a 64-bit control receive table. Value 0 indicates first 32-bit and value 1 indicates last 32-bit of the 64-bit control receive table. |
26:24 | rx_ctrl_seq | RW | 3'b0 | When the Data path width value set to 32: The value in this field determines the 32-bit section of the 32-bit control receive table entry that appears in the RX_CTRL register. Value 0 indicates the first 32-bit section, and value 1 indicates the second 32-bit section and so on. When the Data path width value set to 64: The value in this field determines the 64-bit section of the 64-bit control receive table. You must use this field together with rx_ctrl_wpos filed to target each 32-bit section entry that appears in the RX_CTRL register. Value 0 with rx_ctrl_wpos=0 is the first 32-bit section, value 0 with rx_ctrl_wpos= 1 is the second 32-bit section, value 1 with rx_ctrl_wpos= 0 is the third 32-bit section,value 1 with rx_ctrl_wpos= 1 is the fourth 32-bit section and so on, |
23:16 | rx_ctrl_x | RW | 8'b0 | Index for CPRI control word monitoring (X value in frame location #Z.X.Y). The value in this field determines the control receive table entry of which a 32-bit section appears in the RX_CTRL register. |
15:13 | Reserved | UR0 | 4'b0 | — |
12 | tx_ctrl_wpos | RW | 1'b0 | This field is only available when you set the parameter Data path width value to 64. The value in this field determines the 32-bit section in a 64-bit control transmit table. Value 0 indicates first 32-bit and value 1 indicates last 32-bit of the 64-bit control receive table. |
11 | tx_ctrl_insert | RW | 1'b0 | Control word 32-bit section transmit enable. This value is stored in the control transmit table with its associated entry. When you change the value of the tx_ctrl_seq field or the tx_ctrl_x field, the stored tx_ctrl_insert bit associated with the indexed entry appears in the tx_ctrl_insert field. At the time the CPRI IP core can insert a control transmit table entry in the associated position in the outgoing hyperframe on the CPRI link, if the tx_ctrl_insert bit associated with that entry has the value of 1, and the tx_ctrl_insert_en bit of the L1_CONFIG register is asserted, the IP core inserts the table entry in the hyperframe. |
10:8 | tx_ctrl_seq | RW | 3'b0 | When the Data path width value set to 32: The value in this field determines the 32-bit section of the 32-bit control transmit table entry that appears in the TX_CTRL register. Value 0 indicates the first 32-bit section, and value 1 indicates the second 32-bit section and so on. When the Data path width value set to 64: The value in this field determines the 64-bit section of the 64-bit control transmit table. You must use this field together with tx_ctrl_wpos field to target each 32-bit section entry that appears in the TX_CTRL register. Value 0 with tx_ctrl_wpos=0 is the first 32-bit section, value 0 with tx_ctrl_wpos= 1 is the second 32-bit section, value 1 with tx_ctrl_wpos= 0 is the third 32-bit section,value 1 with tx_ctrl_wpos= 1 is the fourth 32-bit section and so on, |
7:0 | tx_ctrl_x | RW | 8'b0 | Index for CPRI control word insertion (X value in frame location #Z.X.Y). The value in this field determines the control transmit table entry of which a 32-bit section appears in the TX_CTRL register. |
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