CPRI Intel® FPGA IP User Guide

ID 683595
Date 4/04/2022
Public

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5.28. DELAY_CAL_STD_CTRL4 Register

Table 82.  DELAY_CAL_STD_CTRL4 Register at Offset 0x6C This register is available only in CPRI slave Intel® FPGA IP cores with the single-trip delay calibration feature.
Bits Field Name Type Value on Reset Description
31:17 Reserved UR0 15'b0
16 cal_rcv_en RW 1'b0 Enable a CPRI slave IP core to receive TX delay information in incoming CPRI communication.

Software must specify the location of this information in the incoming radio frame by writing the location information in the cal_rcv_seq and cal_rcv_x fields.

The cal_tx_delay_usr_en field of the DELAY_CAL_STD_CTRL5 register overrides this register field.

15 Reserved UR0 1'b0
14:8 cal_rcv_seq RW 7'b0 In a CPRI slave IP core, specifies the sequence number in the incoming basic frame that is the location of the TX delay information provided by the transmitting CPRI master.
Note: If the CPRI master that transmits to this IP core on the CPRI link is an Intel® FPGA CPRI IP core, the value in this field must be identical to the value in the cal_send_seq field of the DELAY_CAL_STD_CTRL3 register in that CPRI master.
7:0 cal_rcv_x RW 8'b0 In a CPRI slave IP core, specifies the basic frame number in the incoming hyperframe that is the location of the TX delay information provided by the transmitting CPRI master.
Note: If the CPRI master that transmits to this IP core on the CPRI link is an Intel® FPGA CPRI IP core, the value in this field must be identical to the value in the cal_send_x field of the DELAY_CAL_STD_CTRL3 register in that CPRI master.

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