CPRI Intel® FPGA IP User Guide

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ID 683595
Date 4/04/2022
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3.8. Direct Vendor Specific Access Interface

If you turn on Enable direct vendor specific access interface in the CPRI parameter editor, the direct vendor specific access interface is available. This interface allows direct access to the Vendor Specific subchannels in the CPRI hyperframe. The Vendor Specific information is present only in subchannels 16 through (P-1) of the CPRI hyperframe, where P is the Fast C&M pointer value. Check the vs_rx_valid and vs_tx_ready signals to ensure you read and write this interface at the time that corresponds to the correct position in the CPRI frame. If you implement the AUX interface, you can read the value on the aux_rx_x or aux_tx_x output signal to identify the current position in the frame.

This interface is Avalon-ST compliant with a ready latency value of 1.

You can alter the transmit latency with the Auxiliary and direct interfaces write latency cycle(s) parameter.

Table 27.  Direct Vendor Specific Access Interface Signals

All interface signals are clocked by the cpri_clkout clock. The Data path width parameter determines the interface type and width, where N= 32 or 64, C= 3 or 7, and D= 31 or 63.

Direct Vendor Specific RX Interface

Signal Name

Direction

Description

vsN_rx_valid[C:0] Output Each asserted bit indicates the corresponding byte on the current vs_rx_data bus is a valid vendor-specific byte.
vsN_rx_data[D:0] Output Vendor-specific word received from the CPRI frame. The vs_rx_valid signal indicates which bytes are valid vendor-specific bytes.
Direct Vendor Specific TX Interface

Signal Name

Direction

Description

vsN_tx_ready[C:0] Output Each asserted bit indicates the IP core is ready to receive a vendor-specific byte from the corresponding byte of vs_tx_data on the next clock cycle.
vsN_tx_valid[C:0] Input Write valid for vs_tx_data. Assert bit [n] of vs_tx_valid to indicate that byte [n] on the vs_tx_data bus holds a valid value in the current clock cycle.
vsN_tx_data[D:0] Input Vendor-specific word to be written to the CPRI frame. The IP core writes the individual bytes of the current value on the vs_tx_data bus to the CPRI frame based on the vs_tx_ready signal from the previous cycle, and the vs_tx_valid signal in the current cycle.
Figure 39. Direct VS RX Timing DiagramDirect VS RX interface behavior in a CPRI IP core running at 0.6144 Gbps.

The aux_rx_x signal is not part of this interface and is available only if you turn on the AUX interface in your CPRI IP variation. However, its presence in the timing diagram explains the timing of the vs_rx_valid output signal that you use to identify the clock cycles with valid VS data.

The aux_rx_x[7:0] signal (labeled simply aux_rx_x) holds the eight-bit index of the basic frame in the hyperframe, from the perspective of the AUX interface. The subchannel index is the control word index modulo 64, available in aux_rx_x[5:0] if you turn on the AUX interface in your CPRI IP core.



Figure 40. Direct VS TX Timing DiagramExpected behavior on the direct VS TX interface of a CPRI IP core running at 0.6144 Gbps.

The aux_tx_x signal is not part of this interface and is available only if you turn on the AUX interface in your CPRI IP variation. However, its presence in the timing diagram explains the timing of the vs_tx_ready output signal that you use to identify the clock cycles when you can write VS data to the CPRI frame.

The aux_tx_x[7:0] signal (labeled simply aux_tx_x) holds the eight-bit index of the basic frame in the hyperframe, from the perspective of the AUX interface. The subchannel index is the control word index modulo 64, available in aux_tx_x[5:0] if you turn on the AUX interface in your CPRI IP core.

Note that the write latency is one cpri_clkout clock cycle in this example.



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