CPRI Intel® FPGA IP User Guide

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ID 683595
Date 4/04/2022
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5.19. TX_DELAY Register

Table 73.  TX_DELAY Register at Offset 0x48
Bits Field Name Type Value on Reset Description
31:9 Reserved UR0 23'b0
8 tx_buf_resync RW 1'b0 Force transmit buffer pointer resynchronization. You can use this register field to resynchronize if, for example, the buffer fill level becomes too high due to due to environmental impacts on the device, such as temperature. Resynchronizing might lead to data loss or corruption.

Do not use this register field to resynchronize after a dynamic CPRI line bit rate change. After a dynamic CPRI line bit rate change the IP core forces resynchronization internally without referring to this register.

7:4 Reserved UR0 4'b0
3:0 tx_buf_delay RO 4'b0 Current transmit buffer fill level.

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