5.2. L1_STATUS Register
|Bits||Field Name||Type||Value on Reset||Description|
|12||rx_rfp_hold||RC||1'b0||Radio frame pulse received. This bit is asserted every 10 ms and remains asserted until cleared by user logic. 6|
|11||rx_freq_alarm_hold||RC||1'b0||CPRI receive clock is not synchronous with main IP core clock (cpri_clkout). This alarm is asserted each time mismatches are found between the recovered CPRI receive clock and cpri_clkout, and remains asserted until cleared by user logic. 6
If you turn on Enable L1 debug interfaces in the CPRI parameter editor, the original asynchronous pulse that sets this register field is visible on the rx_freq_alarm output signal. However, that signal is not available if you turn off Enable L1 debug interfaces.
|10||rx_los_hold||RC||1'b0||Hold rx_los. 6|
|9||rx_err_hold||RC||1'b0||Hold rx_err. 6|
|8||rx_hfnsync_hold||RC||1'b0||Hold rx_hfnsync. 6|
|2||rx_los||RC||1'b1||Indicates receiver is in LOS state.|
|1||rx_err||RC||1'b0||Indicates 8B10B LCV or 64B/66aB sync header violations detected.|
|0||rx_hfnsync||RC||1'b0||Indicates receiver has achieved hyperframe synchronization state (HFNSYNC).|
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