CPRI Intel® FPGA IP User Guide

ID 683595
Date 4/04/2022
Public

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Document Table of Contents

4.3. CPRI Intel® FPGA IP Core Management Interfaces

The CPRI IP core provides multiple interfaces for managing the IP core and the properties of the CPRI link.

Table 51.  CPRI Intel® FPGA IP Core Management Signals

Signal Name

Direction

Description

cpri_clkout Output Main clock signals
cpri_coreclk Input
tx_clkout Output
reset_n Input Main reset signals
reset_rx_n Input
reset_tx_n Input
cpu_clk Input CPU interface
cpu_reset_n Input
cpu_address[15:0]

Input

cpu_byteenable[3:0] Input
cpu_read

Input

cpu_write

Input

cpu_writedata[31:0]

Input

cpu_readdata[31:0]

Output

cpu_waitrequest

Output

cpu_irq

Output

state_startup_seq[2:0] Output Start-up sequence interface

With the exception of the state_l1_synch signal, these signals are available only if you turn on Enable start-up sequence state machine in the CPRI parameter editor.

state_l1_synch[2:0] Output
nego_bitrate_complete Input
nego_protocol_complete Input
nego_cm_complete Input
nego_vss_complete Input
nego_l1_timer_expired Input
nego_bitrate_in[5:0] Input Auto-rate negotiation control and status interface

These signals are available only if you turn on Enable line bit rate auto-negotiation in the CPRI parameter editor.

nego_bitrate_out[5:0] Output
ex_delay_clk Input Extended delay measurement interface
ex_delay_reset_n Input
latency_sclk Input Extended delay measurement interface signals that are available only in Intel® FPGA IP core variations that target an Intel® Stratix® 10 device.
latency_sreset_n Input
cal_status[1:0] Input Single-trip delay calibration interface

This signals are available only if you turn on Enable single-trip delay calibration in the CPRI parameter editor.

cal_ctrl[15:0] Output
rx_lcv Output L1 debug interface

These signals are available only if you turn on Enable L1 debug interfaces in the CPRI parameter editor.

rx_freq_alarm Output