CPRI Intel® FPGA IP User Guide

ID 683595
Date 4/04/2022
Public

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3.6. Direct IQ Interface

If you turn on Enable direct IQ mapping interface in the CPRI parameter editor, the direct IQ interface is available. This interface allows direct access to the I/Q data time slots in the CPRI frame. You can connect this interface to any user-defined air standard I/Q mapping module.

This interface is Avalon-ST compliant with a ready latency value of 1.

You can alter the transmit latency with the Auxiliary and direct interfaces write latency cycle(s) parameter.

Table 25.  Direct IQ Interface SignalsAll interface signals are clocked by the cpri_clkout clock. The Data path width parameter determines the interface type and width, where N= 32 or 64, C= 3 or 7, and D= 31 or 63.
Direct IQ RX Interface

Signal Name

Direction

Description

iqN_rx_valid[C:0] Output Each asserted bit indicates the corresponding byte on the current iq_rx_data bus is valid I/Q data.
iqN_rx_data[D:0] Output I/Q data received from the CPRI frame. The iq_rx_valid signal indicates which bytes are valid I/Q data bytes.
Direct IQ TX Interface

Signal Name

Direction

Description

iqN_tx_ready[C:0] Output Each asserted bit indicates the IP core is ready to read I/Q data from the corresponding byte of iq_tx_data on the next clock cycle.
iqN_tx_valid[C:0] Input Write valid for iq_tx_data. Assert bit [n] to indicate that the corresponding byte on the current iq_tx_data bus is valid I/Q data.
iqN_tx_data[D:0] Input I/Q data to be written to the CPRI frame. The IP core writes the individual bytes of the current value on the iq_tx_data bus to the CPRI frame based on the iq_tx_ready signal from the previous cycle, and the iq_tx_valid signal in the current cycle.
Figure 35. Direct IQ RX Interface Timing DiagramDirect IQ RX interface behavior in a CPRI IP running at 0.6144 Gbps.

The aux_rx_x and aux_rx_seq signals are not part of this interface and are available only if you turn on the AUX interface in your CPRI IP core variation. However, their presence in the timing diagram explains the timing of the iq_rx_valid output signal that you use to identify the clock cycles with valid I/Q data.



Figure 36. Direct IQ TX Interface Timing DiagramExpected behavior on the direct IQ TX interface of a CPRI IP core running at 0.6144 Gbps.

The aux_tx_x and aux_tx_seq signals are not part of this interface and are available only if you turn on the AUX interface in your CPRI IP variation. However, their presence in the timing diagram explains the timing of the iq_tx_ready output signal that you use to identify the clock cycles when you can write I/Q data to the CPRI frame. Note that the write latency is two cpri_clkout clock cycles in this example.



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