CPRI Intel® FPGA IP User Guide

ID 683595
Date 4/04/2022

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5. CPRI Intel® FPGA IP Core Registers

The CPRI IP core internal registers are accessible using the CPU interface, an Avalon-MM interface which conforms to the Avalon Interface Specifications.

All of these registers are 32 bits wide and the addresses are shown as hexadecimal byte address values. The registers can be accessed on a 32-bit (4-byte) basis. The addressing for the registers therefore increments by units of 4.

Write access to a Reserved or undefined location has no effect. Read accesses to a Reserved or undefined location return an undefined result.

Refer to the device specific PHY User Guides for information about the PHY registers.

Table 53.  Register Access CodesLists the access codes used to describe the type of register bits.
Code Description
RW Read / write
RO Read only
RC Read to clear
UR0 Reserved —undefined result on read, no effect on write
Table 54.  Control and Status Register Map
Offset Register Name Function Location of Additional Information
0x00 INTR Interrupt Control and Status INTR Register
0x04 L1_STATUS Layer 1 Status L1_STATUS Register
0x08 L1_CONFIG Layer 1 Configuration L1_CONFIG Register
0x0C BIT_RATE_CONFIG Bit Rate Configuration BIT_RATE_CONFIG Register
0x10 PROT_VER Protocol Version Control and Status PROT_VER Register
0x14 TX_SCR Transmitter Scrambler Control TX_SCR Register
0x18 RX_SCR Receiver Scrambler Status RX_SCR Register
0x1C CM_CONFIG Layer 2 Control and Management Configuration CM_CONFIG Register
0x20 CM_STATUS Layer 2 Control and Management Status CM_STATUS Register
0x24 START_UP_SEQ Start-Up Sequence Control and Status START_UP_SEQ Register
0x28 START_UP_TIMER Start-Up Sequence Timer Control START_UP_TIMER Register
0x2C FLSAR L1 Inband Z.130.0 Control and Status FLSAR Register
0x30 CTRL_INDEX Control Word Index CTRL_INDEX Register
0x34 TX_CTRL Transmit Control Word TX_CTRL Register
0x38 RX_CTRL Receive Control Word RX_CTRL Register
0x3C RX_ERR Receiver Error Status RX_ERR Register
0x40 RX_BFN Recovered Radio Frame Counter RX_BFN Register
0x44 LOOPBACK Loopback Control LOOPBACK Register
0x48 TX_DELAY Transmit Buffer Delay Control and Status TX_DELAY Register
0x4C RX_DELAY Receiver Buffer Delay Control and Status RX_DELAY Register
0x50 TX_EX_DELAY Transmit Buffer Extended Delay Measurement Control and Status TX_EX_DELAY Register
0x54 RX_EX_DELAY Receiver Buffer Extended Delay Measurement Status RX_EX_DELAY Register
0x58 ROUND_TRIP_DELAY Round Trip Delay ROUND_TRIP_DELAY Register
0x5C XCVR_BITSLIP Transceiver Bit Slip Control and Status XCVR_BITSLIP Register
0x60 DELAY_CAL_STD_CTRL1 Single-Trip Delay Calibration Control 1 DELAY_CAL_STD_CTRL1 Register
0x64 DELAY_CAL_STD_CTRL2 Single-Trip Delay Calibration Control 2 DELAY_CAL_STD_CTRL2 Register
0x68 DELAY_CAL_STD_CTRL3 Single-Trip Delay Calibration Control 3 DELAY_CAL_STD_CTRL3 Register
0x6C DELAY_CAL_STD_CTRL4 Single-Trip Delay Calibration Control 4 DELAY_CAL_STD_CTRL4 Register
0x70 DELAY_CAL_STD_CTRL5 Single-Trip Delay Calibration Control 5 DELAY_CAL_STD_CTRL5 Register
0x74 DELAY_CAL_STD_STATUS Single-Trip Delay Calibration Status DELAY_CAL_STD_STATUS Register
0x78 Reserved
0x7C Reserved
0x80 DELAY_CAL_RTD Round Trip Delay Calibration Control and Status DELAY_CAL_RTD Register
0x84 XCVR_TX_FIFO_DELAY Intel® Stratix® 10 H/L-Tile Transmitter FIFO Delay XCVR_TX_FIFO_DELAY Register
0x88 XCVR_RX_FIFO_DELAY Intel® Stratix® 10 H/L-Tile Receiver FIFO Delay XCVR_RX_FIFO_DELAY Register
0x8C IP_INFO IP Information IP_INFO Register
0xA0 DEBUG_STATUS Debug Related Status DEBUG_STATUS Register