CPRI Intel® FPGA IP User Guide

ID 683595
Date 4/04/2022
Public

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4.4. CPRI Intel® FPGA IP Core Transceiver and Transceiver Management Signals

The CPRI IP configures the interface to the CPRI serial link in an Intel® FPGA device transceiver channel. The IP core provides multiple interfaces for managing the transceiver. The transceiver is configured with a Native PHY IP core and exposes many of its optional interfaces for ease of IP core integration in your design.

Table 52.  Transceiver and Transceiver Management Signals

Signal Name

Direction

Description

xcvr_cdr_refclk Input Main transceiver clock and reset-done signals

The tx_analogreset_ack and rx_analogreset_ack signals are available only in Intel® Arria® 10 and Intel® Stratix® 10 variations.

xcvr_recovered_clk Output
xcvr_reset_tx_done Output
xcvr_reset_rx_done Output
tx_analogreset_ack Output
rx_analogreset_ack Output
ehip_ref_clk[1:0] Input
ehip_rst_n 4 Input
ehip_tx_pll_locked 4 Output
xcvr_rxdatain

Input

CPRI link interface
xcvr_txdataout

Output

xcvr_los

Input

reconfig_clk Input 28-nm device transceiver reconfiguration interface

These signals are present only in IP core variations that target an Arria V, Arria V GZ, Cyclone V, or Stratix V device.

reconfig_to_xcvr[69:0] Input
reconfig_from_xcvr[45:0] Output
reconfig_clk Input Intel® Arria® 10 or Intel® Stratix® 10 transceiver reconfiguration interface

These signals are present only in IP core variations that target an Intel® Arria® 10 or Intel® Stratix® 10 device.

reconfig_reset Input
reconfig_write

Input

reconfig_read

Input

reconfig_address[9:0]

Input

reconfig_writedata[31:0]

Input

reconfig_readdata[31:0]

Output

reconfig_waitrequest

Output

reconfig_readdata_valid 4 Output
reconfig_address[10:20] 4 Output
xcvr_tx_analogreset

Input

Interface to external reset controller
xcvr_tx_digitalreset

Input

xcvr_tx_cal_busy

Output

xcvr_rx_analogreset

Input

xcvr_rx_digitalreset

Input

xcvr_rx_cal_busy

Output

xcvr_reset_tx_ready

Input

xcvr_reset_rx_ready

Input

xcvr_rx_analogreset_stat 5 Output
xcvr_rx_digitalreset_stat 5 Output
xcvr_rx_analogreset_stat 5 Output
xcvr_tx_digitalreset_stat 5 Output
xcvr_ext_pll_clk Input Interface to external TX PLL
xcvr_rx_is_lockedtodata Output Transceiver debug interface
xcvr_rx_is_lockedtoref Output Transceiver debug interface

These signals are present only if you turn on Enable L1 debug interfaces in the CPRI parameter editor.

xcvr_rx_errdetect[3:0] Output
xcvr_rx_disperr[3:0] Output
xcvr_rx_blk_sh_err Output
4

This signal is only present in IP core variations that target an Intel® Stratix® 10 E-tile or Intel® Agilex™ E- tile device.

4
5 These signals are present only in Intel® FPGA IP core variation that target an Intel® Stratix® 10 device.

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