CPRI Intel® FPGA IP User Guide

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ID 683595
Date 4/04/2022
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3.19.4. Intel® Arria® 10, Intel® Stratix® 10, and Intel® Agilex™ Transceiver Reconfiguration Interface

If you turn on Management (CSR) interface standard parameter in the CPRI parameter editor, Intel provides a dedicated Avalon® -MM interface, called the transceiver reconfiguration interface, to access the Intel® Arria® 10 or Intel® Stratix® 10 transceiver registers. You access the Native PHY IP core registers through this dedicated interface and not through the IP core general purpose control and status interface. You can recalibrate the PHY through the Avalon-MM interface. You also need to enable this interface for the calibration of the TX PLL. This interface provides access to the hard PCS and the PMA registers of the PHY on the device.

The Avalon-MM interface implements a standard memory-mapped protocol. You can connect an Avalon master to this bus to access the registers of the embedded Native PHY IP core.

In Intel® Stratix® 10 E-tile and Intel® Agilex™ E- tile designs, the Avalon-MM interface is always present regardless of certain parameter settings. This Avalon-MM interface includes three different interfaces CPRI PHY, Native PHY, and RS-FEC3 as shown in figure below.
Figure 64. Reconfiguration Interface Address Map for Intel® Stratix® 10 E-tile and Intel® Agilex™ E- tile Device Variations

Refer to the About the E-Tile CPRI PHY chapter of the E-tile Hard IP User Guide for more information on the Avalon-MM reconfiguration interface.

This interface is available only in variations that target an Intel® Arria® 10 or Intel® Stratix® 10 or and Intel® Agilex™ device, and only if you turn on at least one of these parameters in the CPRI IP core parameter editor:

  • Enable line bit rate auto-negotiation
  • Enable start-up sequence state machine
  • Enable Native PHY Debug Master Endpoint(NPDME), transceiver capability, control and status registers access
  • Enable single-trip delay calibration
Table 43.   CPRI Intel® FPGA IP Core Transceiver Reconfiguration Interface SignalsThe reconfig_clk clocks the signals on the CPRI IP core transceiver reconfiguration interface.

Signal Name

Direction

Description

reconfig_clk Input Clocks the signals on the CPRI transceiver reconfiguration interface. Supports frequency range 100–150 MHz.
reconfig_reset Input Asynchronous active-high reset signal. Resets the CPRI transceiver reconfiguration interface and all of the registers to which it provides access.
reconfig_write

Input

You must assert this signal to request a write transfer.

reconfig_read

Input

You must assert this signal to request a read transfer.

reconfig_address[9:0]

Input

Address for reads and writes.

reconfig_writedata[31:0]

Input

Write data.

reconfig_readdata[31:0]

Output

Read data.

reconfig_waitrequest

Output

The interface is busy. Do not issue Avalon-MM commands to this interface while this signal is high.

reconfig_readdata_valid Output Indicates that the reconfig_readata signal is valid. This port is active only when accessing address 000000 to 07FFFF.

This signal is only present in Intel® Stratix® 10 E-tile and Intel® Agilex™ E- tile device variations.

reconfig_address[10:20] Output Address for reads and writes.

This signal is only present in Intel® Stratix® 10 E-tile and Intel® Agilex™ E- tile device variations.

Figure 65. Read Transaction on the Transceiver Reconfiguration Interface
Figure 66. Write Transaction on the Transceiver Reconfiguration Interface
3 reserved if the IP configuration do not support RS-FEC

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