CPRI Intel® FPGA IP User Guide

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ID 683595
Date 4/04/2022
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2.2. Generating CPRI Intel® FPGA IP Core

You can configure a custom Intel® FPGA IP variation in the parameter editor. Use the following steps to specify CPRI IP core options and parameters in the parameter editor.
Figure 4. IP Parameter Editor
  1. In the Intel® Quartus® Prime Pro Edition software, click File > New Project Wizard to create a new Intel® Quartus® Prime project, or File > Open Project to open an existing Intel® Quartus® Prime project. The wizard prompts you to specify a device. In the Intel® Quartus® Prime Standard Edition software, this step is not required.
  2. In the Intel® FPGA IP Catalog (Tools > IP Catalog), locate and double-click the name CPRI Intel FPGA IP. The parameter editor appears.
  3. Specify a top-level name for your custom Intel® FPGA IP variation. The parameter editor saves the IP variation settings in a file named <your_ip> .ip (in Intel® Quartus® Prime Pro Edition) or <your_ip>.qsys (in Intel® Quartus® Prime Standard Edition). Click OK.
  4. Specify the parameters and options for your IP variation in the parameter editor, including one or more of the following. Refer to CPRI Intel FPGA IP Core Parameters for information about specific IP parameters.
    • Specify parameters defining the IP core functionality, port configurations, and device-specific features.
    • Specify options for processing the IP core files in other EDA tools.
  5. Click Generate HDL. The Generation dialog box appears.
  6. Specify output file generation options, and then click Generate. The IP variation files generate according to your specifications.
  7. To generate a simulation testbench, click Generate Example Design. Please refer to the instructions in the Running the Testbench section.
  8. To generate an HDL instantiation template that you can copy and paste into your text editor, click Generate > Show Instantiation Template.
  9. Click Finish. The parameter editor adds the top-level .qsys or .ip file to the current project automatically. If you are prompted to manually add the .qsys file to the project, click Project > Add/Remove Files in Project to add the file.
    For Intel® Agilex™ F-tile devices, perform these additional steps:
    1. Copy the cpri_ii_tile_ip_gen.tcl from <your_ip>/altera_cpri_ii_c2p_top_<c2p version>/sim/ or <your_ip>/altera_cpri_ii_c2p_top_<c2p_version>/synth/ into the same level as <your_ip>.ip
    2. Execute this file using:
      quartus_sh -t cpri_ii_tile_ip_gen.tcl <your_ip> skip_qtlg
    Few IP cores are generated along a top level wrapper. The wrapper intel_cpri_wrapper.v is the top level file for this IP. The systemclk_f_inst.ip, iopll_sclk_inst.ip and cpriphy_ftile_0.ip are the generated IPs. You must add all these files manually to your Intel® Quartus® Prime project.
  10. After generating and instantiating your IP variation, make appropriate pin assignments to connect ports.

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