CPRI Intel® FPGA IP User Guide

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ID 683595
Date 4/04/2022
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Document Table of Contents
Document Table of Contents x
1. About the CPRI Intel® FPGA IP Core 2. Getting Started with the CPRI Intel® FPGA IP Core 3. Functional Description 4. CPRI Intel® FPGA IP Core Signals 5. CPRI Intel® FPGA IP Core Registers A. Additional Information
1. About the CPRI Intel® FPGA IP Core x
1.1. CPRI Intel® FPGA IP Core Supported Features 1.2. CPRI Intel® FPGA IP Core Device Family and Speed Grade Support 1.3. Intel® FPGA IP Core Verification 1.4. Resource Utilization for CPRI Intel® FPGA IP Core 1.5. Release Information
1.2. CPRI Intel® FPGA IP Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. CPRI Intel® FPGA IP Core Performance: Device and Transceiver Speed Grade Support
2. Getting Started with the CPRI Intel® FPGA IP Core x
2.1. Installation and Licensing 2.2. Generating CPRI Intel® FPGA IP Core 2.3. CPRI Intel® FPGA IP File Structure 2.4. CPRI Intel® FPGA IP Core Parameters 2.5. Integrating Your Intel® FPGA IP Core in Your Design: Required External Blocks 2.6. Simulating Intel FPGA IP Cores 2.7. Understanding the Testbench 2.8. Running the Design Example 2.9. Compiling the Full Design and Programming the FPGA
2.1. Installation and Licensing x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your Intel® FPGA IP Core in Your Design: Required External Blocks x
2.5.1. Adding the Transceiver TX PLL IP Core 2.5.2. Adding the Reset Controller 2.5.3. Adding the Transceiver Reconfiguration Controller 2.5.4. Adding the Off-Chip Clean-Up PLL 2.5.5. Adding and Connecting the Single-Trip Delay Calibration Blocks 2.5.6. Transceiver PLL Calibration 2.5.7. Reference and System PLL Clock for your IP Design
3. Functional Description x
3.1. Interfaces Overview 3.2. CPRI Intel® FPGA IP Core Clocking Structure 3.3. CPRI Intel® FPGA IP Core Reset Requirements 3.4. Start-Up Sequence Following Reset 3.5. AUX Interface 3.6. Direct IQ Interface 3.7. Ctrl_AxC Interface 3.8. Direct Vendor Specific Access Interface 3.9. Real-Time Vendor Specific Interface 3.10. Direct HDLC Serial Interface 3.11. Direct L1 Control and Status Interface 3.12. L1 Debug Interface 3.13. Media Independent Interface (MII) to External Ethernet Block 3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block 3.15. CPU Interface to CPRI Intel® FPGA IP Registers 3.16. Auto-Rate Negotiation 3.17. Extended Delay Measurement 3.18. Deterministic Latency and Delay Measurement and Calibration 3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces 3.20. Testing Features
3.2. CPRI Intel® FPGA IP Core Clocking Structure x
3.2.1. Example CPRI Intel® FPGA IP Core Clock Connections in Different Clocking Modes
3.4. Start-Up Sequence Following Reset x
3.4.1. Start-Up Sequence Interface Signals
3.5. AUX Interface x
3.5.1. AUX Interface Signals 3.5.2. AUX Interface Synchronization 3.5.3. Auxiliary Latency Cycles 3.5.4. Direct Interface CPRI Frame Data Format
3.15. CPU Interface to CPRI Intel® FPGA IP Registers x
3.15.1. CPU Interface Signals 3.15.2. Accessing the Hyperframe Control Words
3.15.2. Accessing the Hyperframe Control Words x
3.15.2.1. Specifying the Control Word 3.15.2.2. Specifying the Position in the Control Word 3.15.2.3. Retrieving the Hyperframe Control Words Control Word Retrieval Example when Data path width is set to 32: Control Word Retrieval Example when Data path width is set to 64: 3.15.2.4. Writing the Hyperframe Control Words
3.17. Extended Delay Measurement x
3.17.1. Extended Delay Measurement for Soft Internal Buffers 3.17.2. Extended Delay Measurement for Intel® Stratix® 10 Hard FIFOs 3.17.3. Extended Delay Measurement Interface
3.18. Deterministic Latency and Delay Measurement and Calibration x
3.18.1. Delay Measurement and Calibration Features 3.18.2. Delay Requirements 3.18.3. Single-Hop Delay Measurement 3.18.4. Multi-Hop Delay Measurement 3.18.5. Delay Calibration Features
3.18.3. Single-Hop Delay Measurement x
3.18.3.1. Rx Path Delay 3.18.3.2. Tx Path Delay 3.18.3.3. Round-Trip Delay
3.18.5. Delay Calibration Features x
3.18.5.1. Single-Trip Delay Calibration 3.18.5.2. Round-Trip Delay Calibration 3.18.5.3. Tx Bitslip Delay
3.18.5.1. Single-Trip Delay Calibration x
3.18.5.1.1. Single-Trip Latency Measurement and Calibration Interface Signals
3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces x
3.19.1. CPRI Link 3.19.2. Main Transceiver Clock and Reset Signals 3.19.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface 3.19.4. Intel® Arria® 10, Intel® Stratix® 10, and Intel® Agilex™ Transceiver Reconfiguration Interface 3.19.5. RS-FEC Interface 3.19.6. Interface to the External Reset Controller 3.19.7. Interface to the External PLL 3.19.8. Transceiver Debug Interface
3.20. Testing Features x
3.20.1. CPRI Intel® FPGA IP Core Loopback Modes 3.20.2. CPRI Intel® FPGA IP Core Self-Synchronization Feature
4. CPRI Intel® FPGA IP Core Signals x
4.1. CPRI Intel® FPGA IP Core L2 Interface 4.2. CPRI Intel® FPGA IP Core L1 Direct Access Interfaces 4.3. CPRI Intel® FPGA IP Core Management Interfaces 4.4. CPRI Intel® FPGA IP Core Transceiver and Transceiver Management Signals
5. CPRI Intel® FPGA IP Core Registers x
5.1. INTR Register 5.2. L1_STATUS Register 5.3. L1_CONFIG Register 5.4. BIT_RATE_CONFIG Register 5.5. PROT_VER Register 5.6. TX_SCR Register 5.7. RX_SCR Register 5.8. CM_CONFIG Register 5.9. CM_STATUS Register 5.10. START_UP_SEQ Register 5.11. START_UP_TIMER Register 5.12. FLSAR Register 5.13. CTRL_INDEX Register 5.14. TX_CTRL Register 5.15. RX_CTRL Register 5.16. RX_ERR Register 5.17. RX_BFN Register 5.18. LOOPBACK Register 5.19. TX_DELAY Register 5.20. RX_DELAY Register 5.21. TX_EX_DELAY Register 5.22. RX_EX_DELAY Register 5.23. ROUND_TRIP_DELAY Register 5.24. XCVR_BITSLIP Register 5.25. DELAY_CAL_STD_CTRL1 Register 5.26. DELAY_CAL_STD_CTRL2 Register 5.27. DELAY_CAL_STD_CTRL3 Register 5.28. DELAY_CAL_STD_CTRL4 Register 5.29. DELAY_CAL_STD_CTRL5 Register 5.30. DELAY_CAL_STD_STATUS Register 5.31. DELAY_CAL_RTD Register 5.32. XCVR_TX_FIFO_DELAY Register 5.33. XCVR_RX_FIFO_DELAY Register 5.34. IP_INFO Register 5.35. DEBUG_STATUS Register
A. Additional Information x
A.1. CPRI Intel® FPGA IP User Guide Archives A.2. Document Revision History for the CPRI Intel® FPGA IP User Guide
1. About the CPRI Intel® FPGA IP Core
2. Getting Started with the CPRI Intel® FPGA IP Core
3. Functional Description
4. CPRI Intel® FPGA IP Core Signals
5. CPRI Intel® FPGA IP Core Registers
A. Additional Information

3.15.2.3. Retrieving the Hyperframe Control Words

A control receive table contains one entry for each of the 256 control words in the current hyperframe. To read a control word, your application must write the control word number X to the rx_ctrl_x field of the CTRL_INDEX register and then read the last received #Z.X control word from the RX_CTRL register. Because the register can hold only 32 bits at a time, depending on the CPRI line bit rate, reading the full control word may require multiple register accesses. Increment the value in the rx_ctrl_seq field of the CTRL_INDEX register from zero to four to access the full control word when the CPRI line bit rate is 10.1376 Gbps, or from zero to two when the CPRI line bit rate is 6.144 Gbps, for example.

Control Word Retrieval Example when Data path width is set to 32:

To retrieve the vendor-specific portion of a control word in the most recent received hyperframe, perform the following steps:

  1. Identify the indices for the vendor-specific portion of the transmit control table, using the formula X = Ns + 64 * Xs.

    In the example, Ns = 16 and Xs = 0, 1, 2, and 3. Therefore, the indices to be read are 16, 80, 144, and 208.

  2. For each value X in 16, 80, 144, and 208, perform the following steps:
    1. Write the value X to the rx_ctrl_x field of the CTRL_INDEX register.
    2. Reset the rx_ctrl_seq field of the CTRL_INDEX register to the value of zero.
    3. In the following cpu_clk cycle, read the first 32-bit section of the control word from the RX_CTRL register.
    4. If the CPRI line bit rate is greater than 2.4576 Gbps, increment the rx_ctrl_seq field of the CTRL_INDEX register to the value of 1 and in the following cpu_clk cycle, read the second 32-bit section of the #Z.X control word from the RX_CTRL register.
    5. If the CPRI line bit rate is greater than 4.9152 Gbps, increment the rx_ctrl_seq field of the CTRL_INDEX register to the value of 2 and in the following cpu_clk cycle, read the third 32-bit section of the #Z.X control word from the RX_CTRL register.
    6. If the CPRI line bit rate is greater than 6.144 Gbps, increment the rx_ctrl_seq field of the CTRL_INDEX register to the value of 3 and in the following cpu_clk cycle, read the fourth 32-bit section of the #Z.X control word from the RX_CTRL register.
    7. If the CPRI line bit rate is 10.1376 Gbps, increment the rx_ctrl_seq field of the CTRL_INDEX register to the value of 4 and in the following cpu_clk cycle, read the fifth 32-bit section of the #Z.X control word (the real-time vendor specific bytes) from the RX_CTRL register.

Control Word Retrieval Example when Data path width is set to 64:

To retrieve the vendor-specific portion of a control word in the most recent received hyperframe, perform the following steps:

  1. Identify the indices for the vendor-specific portion of the transmit control table, using the formula X = Ns + 64 * Xs.

    In the example, Ns = 16 and Xs = 0, 1, 2, and 3. Therefore, the indices to be read are 16, 80, 144, and 208.

  2. For each value X in 16, 80, 144, and 208, perform the following steps:
    1. Write the value X to the rx_ctrl_x field of the CTRL_INDEX register.
    2. Reset the rx_ctrl_seq and rx_ctrl_wpos fields of the CTRL_INDEX register to the value of zero. In the following cpu_clk cycle, read the first 32-bit section of the control word from the RX_CTRL register.
    3. If the CPRI line bit rate is greater than 2.4576 Gbps, increment the rx_ctrl_wpos field of the CTRL_INDEX register to the value of 1 and in the following cpu_clk cycle, read the second 32-bit section of the #Z.X control word from the RX_CTRL register.
    4. If the CPRI line bit rate is greater than 4.9152 Gbps, increment the rx_ctrl_seq and clear the rx_ctrl_wpos field of the CTRL_INDEX register to the value of 1 and 0 respectively. In the following cpu_clk cycle, read the third 32-bit section of the #Z.X control word from the RX_CTRL register.
    5. If the CPRI line bit rate is greater than 6.144 Gbps, increment the rx_ctrl_wpos field of the CTRL_INDEX register to the value of 1 and in the following cpu_clk cycle, read the fourth 32-bit section of the #Z.X control word from the RX_CTRL register.
    6. If the CPRI line bit rate is greater than 9.8304 Gbps, increment the rx_ctrl_seq and clear rx_ctrl_wpos fields of the CTRL_INDEX register to the value of 2 and 0 respectively. In the following cpu_clk cycle, read the fifth 32-bit section of the #Z.X control word from the RX_CTRL register.
    7. If the CPRI line bit rate is 10.1376 Gbps, increment the rx_ctrl_seq field of the CTRL_INDEX register to the value of 1 and in the following cpu_clk cycle, read the sixth 32-bit section of the #Z.X control word (the real-time vendor specific bytes) from the RX_CTRL register.
    8. If the CPRI line bit rate is 24.33024 Gbps, increment the rx_ctrl_seq/rx_ctrl_wpos or clear rx_ctrl_wpos in a similar pattern to access subsequent 32-bit sections from the RX_CTRL register
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