5.3. L1_CONFIG Register
|Bits||Field Name||Type||Value on Reset||Description|
|3||tx_ctrl_insert_en||RW||1'b0||Master enable for insertion of control transmit table entries in CPRI hyperframe. This signal enables control bytes for which the CTRL_INDEX register tx_control_insert bit is high to be written to the CPRI frame.|
|2||tx_enable_force||RW||1'b0||Specifies whether the RE slave self-synchronization testing feature is activated. If the feature is activated, the CPRI RE slave attempts to achieve link synchronization without a CPRI link connection to a CPRI master.
Set this field to the value of 1 to enable the feature. The value of 1 is only valid if the CPRI IP core is configured as a CPRI slave.
|1||synchronization_mode||RW||7||Specifies whether the CPRI IP core is configured as a CPRI slave or a CPRI master, according to the following values:
|0||tx_enable||RW||1'b0||Enable transmission on CPRI link.|
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