CPRI Intel® FPGA IP User Guide

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ID 683595
Date 4/04/2022
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1.4. Resource Utilization for CPRI Intel® FPGA IP Core

Resource utilization changes depending on the parameter settings you specify in the CPRI parameter editor. For example, with every additional interface you enable, the IP core requires additional resources to implement the module that supports that interface.

The resource utilization numbers are approximate as the Intel® Quartus® Prime Fitter assigns resources based on the entirety of your design. The numbers below result from a single run on a simple design. Your results may vary.

Table 4.  Minimum and Maximum IP Core Variations for Resource Utilization Reporting

The IP core FPGA resource utilization table reports resource utilization for a minimum IP core variation and a maximum IP core variation. Parameters not specified remain at their default values, or their values do not affect resource utilization.

Parameter Variation with Minimum Implementation Variation with Maximum Implementation
Line bit rate 1.2288 Gbps for target device in the Intel® Arria® 10, Intel® Stratix® 10, and Intel® Agilex™ device families, 0.6144 Gbps for all other device families Maximum bit rate (device family dependent)
Synchronization mode Master Master
Operation mode TX/RX Duplex TX/RX Duplex
Core clock source input Internal Internal
Receiver soft buffer depth 4 8
Auxiliary and direct interfaces write latency cycle(s) 9
Enable interface, for all optional direct interfaces in the L1 Features tab Off On
Ethernet PCS interface NONE GMII
L2 Ethernet PCS Tx/Rx FIFO depth 11
Enable single-trip delay calibration Off Off
Enable round-trip delay calibration Off On
Round-trip delay calibration FIFO depth 4
Table 5.  CPRI IP Core FPGA Resource UtilizationLists the resources and expected performance for minimum and maximum variations of the CPRI IP core in each supported device family.

For Intel® Agilex™ E-tile, Intel® Stratix® 10, and Intel® Arria® 10 devices, the results are obtained using the Intel® Quartus® Prime Pro Edition software version 20.4.

For Intel® Agilex™ F-tile devices, the results are obtained using the Intel® Quartus® Prime Pro Edition software version 21.2.

For all other target device families, the results are obtained using the Intel® Quartus® Prime Standard Edition software version 17.1.

These numbers were obtained by turning on the Enable Native PHY Debug Master Endpoint(NPDME), transceiver capability, control and status register access parameter.

  • The numbers of ALMs and logic registers are rounded up to the nearest 100.
  • The numbers of ALMs, before rounding, are the ALMs needed numbers from the Intel® Quartus® Prime Fitter Report.
Intel® Agilex™ Device (with F-tile Transceivers) ALMs Logic Registers M20K Blocks
Minimum (2.457 Gbps CPRI line bit rate) 6300 10800 15
Maximum (24.33024 Gbps CPRI line bit rate) 9100 14100 38
Intel® Agilex™ Device (with E-tile Transceivers) ALMs Logic Registers M20K Blocks
Minimum (2.457 Gbps CPRI line bit rate) 4100 6700 10
Maximum (24.33024 Gbps CPRI line bit rate) 10800 13400 40
Intel® Stratix® 10 Device (with E-tile Transceivers) ALMs Logic Registers M20K Blocks
Minimum (2.457 Gbps CPRI line bit rate) 3900 6300 10
Maximum (24.33024 Gbps CPRI line bit rate) 9700 12900 40
Intel® Stratix® 10 Device (with H-and L-tile Transceivers) ALMs Logic Registers M20K Blocks
Minimum (1.2288 Gbps CPRI line bit rate) 1400 2200 3
Maximum (24.33024 Gbps CPRI line bit rate) 17900 32100 47
Intel® Arria® 10 Device ALMs Logic Registers M20K Blocks
Minimum (1.2288 Gbps CPRI line bit rate) 1000 2000 2
Maximum (12.16 Gbps CPRI line bit rate) 6600 9600 24

Arria V GX or GT Device

ALMs

Logic Registers

M10K Blocks

Minimum (0.6144 Gbps CPRI line bit rate)

900 1600 6

Maximum (6.144 Gbps CPRI line bit rate)

3200 5000 15

Arria V GZ Device

ALMs

Logic Registers

M20K Blocks

Minimum (0.6144 Gbps CPRI line bit rate)

1000 1600 2

Maximum (9.8304 Gbps CPRI line bit rate)

3300 5100 9

Cyclone V GX or GT Device

ALMs

Logic Registers

M10K Blocks

Minimum (0.6144 Gbps CPRI line bit rate)

900 1600 6

Maximum (4.9512 Gbps CPRI line bit rate)

3100 5000 11

Stratix V GX or GT Device

ALMs

Logic Registers

M20K Blocks

Minimum (0.6144 Gbps CPRI line bit rate)

900 1600 2

Maximum (10.1376 Gbps CPRI line bit rate)

3900 6000 18

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