5.25. DELAY_CAL_STD_CTRL1 Register
|Bits||Field Name||Type||Value on Reset||Description|
|16||cal_reset||RW||1'b0||Reset single-trip delay calibration.
Set this bit to the value of 1 to reset the IP core single-trip delay calibration module and the Intel® -provided DPCU module that you have connected to the IP core. Reset this bit to the value of 0 to resume the normal functionality of these two modules.
Setting this bit to the value of 1 resets all of the single-trip delay calibration logic. This reset does not affect the values in the DELAY_CAL_STD_CTRLn registers. However, the reset does override the value in the cal_int_check field.
|8||cal_int_check||RW||1'b0||Enable single-trip delay consistency checking. If you set this bit to the value of 1, the IP core checks once per hyperframe that the sum of the cal_step_delay and cal_cycle_delay field values in the DELAY_CAL_STD_CTRL2 register match the cal_current_delay field value in the DELAY_CAL_STD_STATUS register. If they do not match, the IP core triggers recalibration.
If you set this bit to the value of 0, the IP core performs a consistency check only when you set the cal_en bit. If cal_int_check has the value of 0, the user can schedule consistency checks by resetting and setting the cal_en bit.
|0||cal_en||RW||1'b0||Enable single-trip delay calibration.
Set this bit to the value of 1 to activate single-trip delay calibration. Reset this bit to the value of 0 to turn off single-trip delay calibration.
Did you find the information on this page useful?