CPRI Intel® FPGA IP User Guide

ID 683595
Date 4/04/2022
Public

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5.4. BIT_RATE_CONFIG Register

Table 58.  BIT_RATE_CONFIG Register at Offset 0x0C
Bits Field Name Type Value on Reset Description
31:5 Reserved UR0 27'b0
5:0 bit_rate 8 9 CPRI line bit rate to be used in next attempt to achieve frame synchronization, encoded according to the following valid values:
  • 6'b000001: 0.6144 Gbps
  • 6'b000010: 1.2288 Gbps
  • 6'b000100: 2.4576 Gbps
  • 6'b000101: 3.0720 Gbps
  • 6'b001000: 4.9150 Gbps
  • 6'b001010: 6.1440 Gbps
  • 6'b001100: 8.11008 Gbps
  • 6'b010000: 9.8304 Gbps
  • 6'b010100: 10.1376 Gbps
  • 6b'011000: 12.16512 Gbps
  • 6'b110000 : 24.33024 Gbps

If the input signal nego_bitrate_in has a non-zero value, the CPRI IP core uses the encoded value driven on nego_bitrate_in in the next attempt to achieve frame synchronization, and ignores the value in the bit_rate register field.

The value driven on the nego_bitrate_in signal, if it is non-zero, always overrides the value in this register field.

8 If you turn on Enable line bit rate auto-negotiation, this register field is a RW register field. If you turn off Enable line bit rate auto-negotiation, this register field is a RO register field.
9 Reset value is the value you specify for Line bit rate in the CPRI parameter editor.

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