CPRI Intel® FPGA IP User Guide

ID 683595
Date 4/04/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.18.5. Delay Calibration Features

The CPRI Intel® FPGA IP provides multiple calibration features to support compliance with the CPRI Specification.
  • If you turn on Enable single-trip delay calibration in the CPRI parameter editor, supports single-trip delay calibration using the DELAY_CAL_STD_CTRL1, DELAY_CAL_STD_CTRL2, DELAY_CAL_STD_CTRL3, DELAY_CAL_STD_CTRL3, DELAY_CAL_STD_CTRL4, DELAY_CAL_STD_CTRL5, and DELAY_CAL_STD_STATUS registers. You can connect the IOPLL and DPCU blocks that Intel® provides with the CPRI IP core to ensure correct calibration results.
  • If you turn on Enable round-trip delay calibration in the CPRI parameter editor, supports round-trip delay calibration using the DELAY_CAL_RTD register.
  • In all supported device families, increases the consistency of the round-trip delay using the XCVR_BITSLIP register.

Did you find the information on this page useful?

Characters remaining:

Feedback Message