CPRI Intel® FPGA IP User Guide

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ID 683595
Date 4/04/2022
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5.8. CM_CONFIG Register

Table 62.  CM_CONFIG Register at Offset 0x1C
Bits Field Name Type Value on Reset Description
31:13 Reserved UR0 19'b0
12 slow_cm_rate_auto RW 1'b1 Enable auto-negotiation of HDLC rate.

If you turn on Enable protocol version and C&M channel setting auto-negotiation, this field is a RW register field with the default value of 1. Otherwise, this field is a RO register field with the default value of 0.

RO 1'b0
11 slow_cm_rate_filter RW 1'b1 Enable filtering of HDLC rate.
10:8 tx_slow_cm_rate RW 3'b110 Rate configuration for slow Control and Management (HDLC). To be inserted in CPRI control byte Z.66.0.
7 fast_cm_ptr_auto RW 1'b1 Enable auto-negotiation of Ethernet rate.

If you turn on Enable protocol version and C&M channel setting auto-negotiation, this field is a RW register field with the default value of 1. Otherwise, this field is a RO register field with the default value of 0.

RO 1'b0
6 fast_cm_ptr_filter RW 1'b1 Enable filtering of Ethernet rate.
5:0 tx_fast_cm_ptr RW 6'd20 Pointer to first CPRI control word used for fast Control and Management (Ethernet). To be inserted in CPRI control byte Z.194.0.

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