CPRI Intel® FPGA IP User Guide

ID 683595
Date 4/04/2022
Public

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5.35. DEBUG_STATUS Register

Table 89.  DEBUG_STATUS Register at Offset 0xA0
Bits Field Name Type Value on Reset Description
31:5 Reserved UR0 24'b0 -
4 S10E_HI_BER RO 1'h0 Indicates RX PCS Hi BER state.
3 S10E_LANE_STABLE RO 1'h0 Indicates that the TX PMA is ready.
2 S10E_BLOCK_LOCK RO 1'h0 Indicates the block alignment has been finished.
1 S10E_RX_PCS_READY RO 1'h0 The RX data path is ready to receive data. This bit is valid when 64b/66b path is used.
0 S10E_READY RO 1'h0 Indicates that the CPRI PHY has completed all its internal initialization activities and it is ready to accept reconfiguration transactions. It also indicates that the TX data path is ready to send the data. This bit is valid when 64b/66b path is used.

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