CPRI Intel® FPGA IP User Guide

ID 683595
Date 4/04/2022

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3.10. Direct HDLC Serial Interface

If you turn on Enable direct HDLC serial interface in the CPRI parameter editor, the direct HDLC serial interface is available. This interface allows direct access to the slow control and management data in the CPRI frame. You can connect this interface to a user-defined HDLC PCS and MAC.

This interface is Avalon-ST compliant with a ready latency value of 1.

You can alter the transmit write latency with the Auxiliary and direct interfaces write latency cycle(s) parameter. However, you do not need to view the aux_tx_seq signal for correct alignment. You can monitor the hdlc_rx_valid and hdlc_tx_ready signals to discover the correct times to read and write data on this interface.

Table 29.  Direct HDLC Serial Interface SignalsAll interface signals are clocked by the cpri_clkout clock.
Direct HDLC Serial RX Interface

Signal Name



hdlc_rx_valid Output When asserted, indicates hdlc_rx_data holds a valid HDLC bit in the current clock cycle.
hdlc_rx_data Output HDLC data stream received from the CPRI frame. The hdlc_rx_valid signal indicates which bits are valid HDLC bytes.
Direct HDLC Serial TX Interface

Signal Name



hdlc_tx_ready Output When asserted, indicates the IP core is ready to receive HDLC data from hdlc_tx_data on the next clock cycle.
hdlc_tx_valid Input Write valid for hdlc_tx_data. Assert this signal to indicate that hdlc_tx_data holds a valid HDLC bit in the current clock cycle.
hdlc_tx_data Input HDLC data stream to be written to the CPRI frame directly. The IP core writes the current value on hdlc_tx_data to the CPRI frame based on the hdlc_tx_ready signal from the previous cycle, and the hdlc_tx_valid signal in the current cycle.
Figure 43. Direct HDLC Serial RX Timing DiagramHDLC Serial RX interface behavior in a CPRI IP core running at 0.6144 Gbps.

Figure 44. Direct HDLC Serial TX Timing DiagramExpected behavior on the HDLC Serial TX interface of a CPRI IP core running at 0.6144 Gbps.

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