CPRI Intel® FPGA IP User Guide

ID 683595
Date 4/04/2022
Public

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3.19.2. Main Transceiver Clock and Reset Signals

Table 41.  Main Transceiver Clock and Reset-Done SignalsThe clocks for individual interfaces are listed with the relevant interface signals.

Signal Name

Direction

Description

xcvr_cdr_refclk Input Receiver CDR reference clock. You must drive this clock at the frequency you specified for the Receiver CDR reference clock frequency (MHz) parameter in the CPRI parameter editor.

For the list of CDR frequency available based on line bit rate, refer to CPRI Intel FPGA IP Core Parameters.

This signal is not present in IP core variations that target an Intel® Stratix® 10 E-tile and Intel® Agilex™ E- tile device.

xcvr_recovered_clk Output Direct recovered clock from the receiver CDR. Use this output clock to drive the external clean-up PLL when your IP core is in slave mode. This clock is present only in CPRI Intel® FPGA IP cores in slave clocking mode with Operation mode set to the value of RX/TX Duplex or RX Simplex.
xcvr_reset_tx_done Output Indicates the transmitter and IP core Tx path have completed the internal reset sequence. This signal is clocked by the cpri_clkout clock.
xcvr_reset_rx_done Output Indicates the receiver and Intel® FPGA IP core Rx path have completed the internal reset sequence. This signal is clocked by the cpri_clkout clock.
tx_analogreset_ack Output This signal rises after the TX analog reset process completes. This signal falls after you deassert the tx_analogreset signal.This signal is asynchronous. Refer to Resetting Transceiver Channels in the Intel® Arria® 10 Transceiver PHY User Guide.

This signal is available in CPRI IP cores that target an Intel® Arria® 10 device. Your custom auto-rate negotiation logic can monitor this signal to determine when it can safely begin reconfiguring the device transceiver to a new CPRI line bit rate.

rx_analogreset_ack Output This signal rises after the RX analog reset process completes. This signal falls after you deassert the rx_analogreset signal. This signal is asynchronous. Refer to Resetting Transceiver Channels in the Intel® Arria® 10 Transceiver PHY User Guide.

This signal is available in CPRI Intel® FPGA IP cores that target an Intel® Arria® 10 device. Your custom auto-rate negotiation logic can monitor this signal to determine when it can safely begin reconfiguring the device transceiver to a new CPRI line bit rate.

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