Intel® Quartus® Prime Standard Edition User Guide: Debug Tools

ID 683552
Date 9/24/2018
Document Table of Contents Generating reconfig_clk from an Internal PLL

You can use an internal PLL to generate the reconfig_clk, by changing the Platform Designer (Standard) connections to delay offset cancellation until the generated clock is stable.
  • If there is no free running clock within the required frequency range of the reconfiguration clock, add a PLL to the top-level of the design example. The frequency range varies depending on the device family. Refer to the device family data sheet for your device.
  • When using an internal PLL, hold off offset cancellation until the generated clock is stable. You do this by connecting the pll_locked signal of the internal PLL to the .clk_clk_in_reset_n port of the Platform Designer (Standard) system, instead of the system_reset signal.
  • Implement the filter logic, inverter, and synchronization to the reconfig_clk outside of the Platform Designer (Standard) system with your own logic.

You can find the support solution in the Intel FPGA Knowledge Base. The solution applies to only Arria® V, Cyclone® V, Stratix® IV GX/GT, and Stratix® V devices.