Intel® Quartus® Prime Standard Edition User Guide: Debug Tools

ID 683552
Date 9/24/2018
Document Table of Contents Signal Preservation

The Intel® Quartus® Prime software provides synthesis attributes that prevent the Compiler from performing optimizations on specific signals, allowing them to persist into the post-fit netlist.

The Intel® Quartus® Prime software optimizes the RTL signals during synthesis and place-and-route. RTL signal names may not appear in the post-fit netlist after optimizations.

The optimization attributes are:

  • keep—Prevents removal of combinational signals during optimization.
  • preserve—Prevents removal of registers during optimization.

However, preserving attributes can increase device resource utilization or decrease timing performance.

Note: These processing results can cause problems with the incremental compilation flow in Signal Tap Logic Analyzer. Because you can only add post-fitting signals to the Signal Tap Logic Analyzer in partitions of type post-fit, RTL signals that you want to monitor may not be available, preventing their use. To avoid this issue, add synthesis attributes that preserve signals during synthesis and place-and-route.

Preserving nodes is often necessary when you add groups of signals for an IP with a plug-in. If you are debugging an encrypted IP core, such as the Nios® II CPU, you might need to preserve nodes from the core to keep available for debugging with the Signal Tap Logic Analyzer.

In incremental compilation flows, pre-synthesis nodes may not be connected to the Signal Tap Logic Analyzer for post-fit partitions. Signal Tap issues a critical warning for all pre-synthesis node names that do not exist in the post-fit netlist.

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