Intel® Quartus® Prime Standard Edition User Guide: Debug Tools

ID 683552
Date 9/24/2018
Document Table of Contents Input Port Mode

When using the Input port mode, the Signal Tap Logic Analyzer takes any signal from your design as an input. During acquisition, if the signal is high on the clock edge, the Signal Tap Logic Analyzer stores the data in the buffer. If the signal is low on the clock edge, the Logic Analyzer ignores the data sample. If you don't specify an internal node, the Logic Analyzer creates and connects a pin to this input port.

If you are creating a Signal Tap Logic Analyzer instance through an .stp file, specify the storage qualifier signal using the input port field located on the Setup tab. You must specify this port for your project to compile.

If you use the parameter editor, the storage qualification input port, if specified, appears in the generated instantiation template. You can then connect this port to a signal in your RTL.

Figure 47. Comparing Continuous and Input Port Capture Mode in Data Acquisition of a Recurring Data Pattern
  • Continuous Mode:
  • Input Port Storage Qualifier: