Intel® Quartus® Prime Standard Edition User Guide: Debug Tools

ID 683552
Date 9/24/2018
Document Table of Contents Additional Considerations for State Machines in Signal Tap

  • The Signal Tap configuration GUI recognizes state machines from your design only if you use Intel® Quartus® Prime Integrated Synthesis. Conversely, the state machine debugging feature is not able to track the FSM signals or state encoding if you use other EDA synthesis tools.
  • If you add post-fit FSM signals, the Signal Tap Logic Analyzer FSM debug feature may not track all optimization changes that are a part of the compilation process.
  • If the following two specific optimizations are enabled, the Signal Tap FSM debug feature may not list mnemonic tables for state machines in the design:
    • If you enabled the Physical Synthesis optimization, state registers may be resource balanced (register retiming) to improve fMAX. The FSM debug feature does not list post-fit FSM state registers if register retiming occurs.
    • The FSM debugging feature does not list state signals that the Compiler packed into RAM and DSP blocks during synthesis or Fitter optimizations.
  • You can still use the FSM debugging feature to add pre-synthesis state signals.