Intel® Quartus® Prime Standard Edition User Guide: Debug Tools

ID 683552
Date 9/24/2018
Document Table of Contents

3.3.3. Instantiating and Parameterizing Intel® Arria® 10 Debug IP cores

To debug Intel® Arria® 10 designs with the Transceiver Toolkit, you must enable debugging settings in Transceiver Intel® FPGA IP cores. You can either activate these settings when you first instantiate these components, or modify your instance after preliminary compilation.
The IP cores that you modify are:
  • Transceiver Native PHY
  • Transceiver ATX PLL
  • fPLL

The parameters that you enable in the debug IP cores are:

Table 38.  IP Cores and Debug SettingsFor more information about these parameters, refer to Debug Settings for Transceiver IP Cores.
IP Core Enable dynamic reconfiguration Enable Altera Debug Master Endpoint Enable capability registers Enable control and status registers Enable PRBS Soft accumulators
Transceiver Native PHY Yes Yes Yes Yes Yes
Transceiver ATX PLL Yes Yes      
CMU PLL Yes Yes      
fPLL Yes Yes      
For each transceiver IP core:
  1. In the IP Components tab of the Project Navigator, right-click the IP instance, and click Edit in Parameter Editor.
  2. Turn on debug settings as they appear in the IP Cores and Debug Settings table above.
    Figure 22.  Intel® Arria® 10 Transceiver Native PHY IP Core in the Parameter Editor
    Figure 23.  Intel® Arria® 10 Transceiver ATX PLL Core in the Parameter Editor
  3. Click Generate HDL.
After enabling parameters for all IPs in the design, recompile your project.