Visible to Intel only — GUID: mwh1410384354040
Ixiasoft
Visible to Intel only — GUID: mwh1410384354040
Ixiasoft
3.3.2.4. Link Optimization Test Configuration ( Stratix® V)
From | To | ||
---|---|---|---|
Your Design Logic |
Data Pattern Generator bypass port |
||
Data Pattern Generator |
PHY input port |
||
JTAG to Avalon® Master Bridge |
Altera Avalon® Data Pattern Generator |
||
JTAG to Avalon® Master Bridge |
Altera Avalon® Data Pattern Checker |
||
Data Pattern Checker |
PHY output port |
||
JTAG to Avalon® Master Bridge |
Transceiver Reconfiguration Controller |
||
JTAG to Avalon® Master Bridge |
PHY input port |
||
Transceiver Reconfiguration Controller |
PHY input port |
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