Intel® Quartus® Prime Standard Edition User Guide: Debug Tools

ID 683552
Date 9/24/2018
Document Table of Contents Signal Tap Logic in Critical Path

If Signal Tap logic is part of your critical path, follow these tips to speed up the performance of the Signal Tap Logic Analyzer:

  • Disable runtime configurable options—Certain resources are allocated to accommodate for runtime flexibility. If you use either advanced triggers or State-based triggering flow, disable runtime configurable parameters for a boost in fMAX of the Signal Tap logic.
    • If you are using State-based triggering flow, try disabling the Goto state destination option and performing a recompilation before disabling the other runtime configurable options. The Goto state destination option has the greatest impact on fMAX, as compared to the other runtime configurable options.
  • Minimize the number of signals that have Trigger Enable selected—By default, Signal Tap Logic Analyzer enable the Trigger Enable option for all signals that you add to the .stp file. For signals that you do not plan to use as triggers, turn this option off.
  • Turn on Physical Synthesis for register retiming—If many (more than the number of inputs that fit in a LAB) enabled triggering signals fan-in logic to a gate-based triggering condition (basic trigger condition or a logical reduction operator in the advanced trigger tab), turn on Perform register retiming. This can help balance combinational logic across LABs.