Visible to Intel only — GUID: mwh1410384413200
Ixiasoft
Visible to Intel only — GUID: mwh1410384413200
Ixiasoft
4.1.4. Add Registers Between Pipeline Paths and Signal Probe Pins
You can specify the number of registers placed between a Signal Probe source and a Signal Probe pin. The registers synchronize data to a clock and control the latency of the Signal Probe outputs. The Signal Probe feature automatically inserts the number of registers specified into the Signal Probe path.
The figure shows a single register between the Signal Probe source Reg_b_1 and Signal Probe Signal Probe_Output_2 output pin added to synchronize the data between the two Signal Probe output pins.
In addition to clock input for pipeline registers, you can also specify a reset signal pin for pipeline registers. To specify a reset pin for pipeline registers, use the Tcl command make_sp.