Intel® Quartus® Prime Standard Edition User Guide: Debug Tools

ID 683552
Date 9/24/2018
Document Table of Contents

1.1.1. System Debugging Tools Comparison

Table 1.  System Debugging Tools Portfolio
Tool Description Typical Usage
System Console
  • Provides real-time in-system debugging capabilities.
  • Allows you to read from and write to Memory Mapped components in a system without a processor or additional software
  • Communicates with hardware modules in a design through a Tcl interpreter.
  • Allows you to take advantage of all the features of the Tcl scripting language.
  • Supports JTAG and TCP/IP connectivity.

You need to perform system-level debugging.

For example, if you have an Avalon® -MM slave or Avalon® -ST interfaces, you can debug the design at a transaction level.

Transceiver Toolkit
  • Allows you to test and tune transceiver link signal quality through a combination of metrics.
  • Auto Sweeping of physical medium attachment (PMA) settings help you find optimal parameter values.
You need to debug or optimize signal integrity of a board layout even before finishing the design.
Signal Tap Logic Analyzer
  • Uses FPGA resources.
  • Samples test nodes, and outputs the information to the Intel® Quartus® Prime software for display and analysis.
You have spare on-chip memory and you want functional verification of a design running in hardware.
Signal Probe Incrementally routes internal signals to I/O pins while preserving results from the last place-and-routed design. You have spare I/O pins and you want to check the operation of a small set of control pins using either an external logic analyzer or an oscilloscope.
Logic Analyzer Interface (LAI)
  • Multiplexes a larger set of signals to a smaller number of spare I/O pins.
  • Allows you to select which signals switch onto the I/O pins over a JTAG connection.
You have limited on-chip memory and a large set of internal data buses to verify using an external logic analyzer. Logic analyzer vendors, such as Tektronics* and Agilent*, provide integration with the tool to improve usability.
In-System Sources and Probes Provides an easy way to drive and sample logic values to and from internal nodes using the JTAG interface. You want to prototype the FPGA design using a front panel with virtual buttons.
In-System Memory Content Editor Displays and allows you to edit on-chip memory.

You want to view and edit the contents of on-chip memory that is not connected to a Nios® II processor.

You can also use the tool when you do not want to have a Nios® II debug core in your system.

Virtual JTAG Interface Allows you to communicate with the JTAG interface so that you can develop custom applications. You want to communicate with custom signals in your design.

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