5.3.1. Assigning an Acquisition Clock
You can use any signal in your design as the acquisition clock. However, for best results in data acquisition, use a global, non-gated clock that is synchronous to the signals under test. Using a gated clock as your acquisition clock can result in unexpected data that does not accurately reflect the behavior of your design. The Intel® Quartus® Prime static timing analysis tools show the maximum acquisition clock frequency at which you can run your design. To find the maximum frequency of the logic analyzer clock, refer to the Timing Analysis section of the Compilation Report.
If you do not assign an acquisition clock in the Signal Tap Logic Analyzer Editor, Intel® Quartus® Prime software automatically creates a clock pin called auto_stp_external_clk. You must make a pin assignment to this pin, and make sure that a clock signal in your design drives the acquisition clock.
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