Intel® Quartus® Prime Standard Edition User Guide: Debug Tools

ID 683552
Date 9/24/2018
Document Table of Contents

5.5.5. Timing Preservation with the Signal Tap Logic Analyzer

In addition to verifying functionality, timing closure is one of the most crucial processes in successful operation of a design.
Note: When you compile a project with a Signal Tap Logic Analyzer without the use of incremental compilation, you must add IP to the existing design. This addition often impacts the existing placement, routing, and timing of the design. To minimize the effect that the Signal Tap Logic Analyzer has on the design, use incremental compilation for the project. Incremental compilation is the default setting in new designs. You can easily enable incremental compilation in existing designs. When the Signal Tap Logic Analyzer is in a design partition, it has little to no affect on the design.

For Intel® Arria® 10 devices, the Intel® Quartus® Prime Standard Edition software does not support timing preservation for post-fit taps with Rapid Recompile.

The following techniques can help you maintain timing:

  • Avoid adding critical path signals to the .stp file.
  • Minimize the number of combinational signals you add to the .stp file, and add registers whenever possible.
  • Specify an fMAX constraint for each clock in the design.