Intel® Quartus® Prime Standard Edition User Guide: Debug Tools

ID 683552
Date 9/24/2018
Document Table of Contents

4.1. Design Flow Using Signal Probe

The Signal Probe feature allows you to reserve available pins and route internal signals to those reserved pins, while preserving the behavior of your design. Signal Probe is an effective debugging tool that provides visibility into your FPGA.

You can reserve pins for Signal Probe and assign I/O standards after a full compilation. Each Signal Probe-source to Signal Probe-pin connection is implemented as an engineering change order (ECO) that is applied to your netlist after a full compilation.

To route the internal signals to the device’s reserved pins for Signal Probe, perform the following tasks:

  1. Perform a full compilation.
  2. Reserve Signal Probe Pins.
  3. Assign Signal Probe sources.
  4. Add registers between pipeline paths and Signal Probe pins.
  5. Perform a Signal Probe compilation.
  6. Analyze the results of a Signal Probe compilation.