Intel® Quartus® Prime Standard Edition User Guide: Debug Tools

ID 683552
Date 9/24/2018
Document Table of Contents Debug Settings for Transceiver IP Cores

The table describes the settings that you turn on when preparing your transceiver for debug:

Table 39.   Intel® FPGA IP Settings for Transceiver Debug
Setting Description
Enable Dynamic Reconfiguration Allows you to change the behavior of the transceiver channels and PLLs without powering down the device
Enable Altera Debug Master Endpoint Allows you to access the transceiver and PLL registers through System Console. When you recompile your design, Intel® Quartus® Prime software inserts the ADME, debug fabric, and embedded logic during synthesis.
Enable capability registers Capability registers provide high level information about the configuration of the transceiver channel
Enable control and status registers Enables soft registers to read status signals and write control signals on the PHY interface through the embedded debug.
Enable PRBS Soft Accumulators Enables soft logic for performing PRBS bit and error accumulation when you use the hard PRBS generator and checker.

For more information about dynamic reconfiguration parameters on Intel® Arria® 10 devices, refer to the Intel® Arria® 10 Transceiver PHY User Guide .