Visible to Intel only — GUID: mwh1410384511711
Ixiasoft
Visible to Intel only — GUID: mwh1410384511711
Ixiasoft
5.3.4. Adding Finite State Machine State Encoding Registers
Finding the signals to debug finite state machines (FSM) can be challenging. Finding nodes from the post-fit netlist may be impossible, since the Compiler may change or optimize away FSM encoding signals. To find and map FSM signal values to the state names that you specified in your HDL, you must perform an additional step.
The Signal Tap Logic Analyzer can detect FSMs in your compiled design. The configuration automatically tracks the FSM state signals as well as state encoding through the compilation process.
To add all the FSM state signals to your logic analyzer with a single command Shortcut menu commands allow you .
For each FSM added to your Signal Tap configuration, the FSM debugging feature adds a mnemonic table to map the signal values to the state enumeration that you provided in your source code. The mnemonic tables enable you to visualize state machine transitions in the waveform viewer. The FSM debugging feature supports adding FSM signals from both the pre-synthesis and post-fit netlists.
Section Content
Modify and Restore Mnemonic Tables for State Machines
Additional Considerations for State Machines in Signal Tap