Intel® Quartus® Prime Standard Edition User Guide: Debug Tools

ID 683552
Date 9/24/2018
Document Table of Contents Custom Trigger HDL Module Properties

Table 58.  Custom Trigger HDL Module Properties
Property Description
Custom HDL Module Name Module name of the triggering logic.
Configuration Bitstream
  • Allows to create trigger logic that you can configure at runtime, based upon the value of the configuration bitstream.
  • The Signal Tap logic analyzer reads the configuration bitstream property as binary, therefore the bitstream must contain only the characters 1 and 0.
  • The bit-width (number of 1s and 0s) must match the pattern_in bit width.
  • A blank configuration bitstream implies that the module does not have a pattern_in input.

Specifies the number of pipeline stages in the triggering logic.

For example, if after receiving a triggering input the LA needs three clock cycles to assert the trigger output, you can denote a pipeline value of three.

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