Intel® Quartus® Prime Standard Edition User Guide: Debug Tools

ID 683552
Date 9/24/2018
Document Table of Contents Sequential Triggering

When you specify a sequential trigger the Signal Tap Logic Analyzer sequentially evaluates each the conditions. The sequential triggering flow allows you to cascade up to 10 levels of triggering conditions.

When the last triggering condition evaluates to TRUE, the Signal Tap Logic Analyzer starts the data acquisition. For segmented buffers, every acquisition segment after the first starts on the last condition that you specified. The Simple Sequential Triggering feature allows you to specify basic triggers, comparison triggers, advanced triggers, or a mix of all three.

Figure 68. Sequential Triggering FlowThe figure illustrates the simple sequential triggering flow for non-segmented and segmented buffers.

Notes to figure:

  1. The acquisition buffer starts capture when all n triggering levels are satisfied, where n <10.

The Signal Tap Logic Analyzer considers external triggers as level 0, evaluating external triggers before any other trigger condition.