Intel® Quartus® Prime Standard Edition User Guide: Debug Tools

ID 683552
Date 9/24/2018
Document Table of Contents

5.1.2. Signal Tap Logic Analyzer Features and Benefits

Feature Benefit
Quick access toolbar Provides single-click operation of commonly-used menu items. You can hover over the icons to see tool tips.
Multiple logic analyzers in a single device Allows you to capture data from multiple clock domains in a design at the same time.
Multiple logic analyzers in multiple devices in a single JTAG chain Allows you to capture data simultaneously from multiple devices in a JTAG chain.
Nios® II plug-in support Allows you to specify nodes, triggers, and signal mnemonics for IP, such as the Nios® II processor.
Up to 10 basic, comparison, or advanced trigger conditions for each analyzer instance Allows you to send complex data capture commands to the logic analyzer, providing greater accuracy and problem isolation.
Power-up trigger Captures signal data for triggers that occur after device programming, but before manually starting the logic analyzer.
Custom trigger HDL object You can code your own trigger in Verilog HDL or VHDL and tap specific instances of modules located anywhere in the hierarchy of your design, without needing to manually route all the necessary connections. This simplifies the process of tapping nodes spread out across your design.
State-based triggering flow Enables you to organize your triggering conditions to precisely define what your logic analyzer captures.
Incremental compilation Allows you to modify the signals and triggers that the Signal Tap Logic Analyzer monitors without performing a full compilation, saving time.
Incremental route with rapid recompile Allows you to manually allocate trigger input, data input, storage qualifier input, and node count, and perform a full compilation to include the Signal Tap Logic Analyzer in your design. Then, you can selectively connect, disconnect, and swap to different nodes in your design. Use Rapid Recompile to perform incremental routing and gain a 2-4x speedup over the initial full compilation.
Flexible buffer acquisition modes The buffer acquisition control allows you to precisely control the data that is written into the acquisition buffer. Both segmented buffers and non-segmented buffers with storage qualification allow you to discard data samples that are not relevant to the debugging of your design.
MATLAB* integration with included MEX function Collects the data the Signal Tap Logic Analyzer captures into a MATLAB* integer matrix.
Up to 2,048 channels per logic analyzer instance Samples many signals and wide bus structures.
Up to 128K samples per instance Captures a large sample set for each channel.
Fast clock frequencies Synchronous sampling of data nodes using the same clock tree driving the logic under test.
Resource usage estimator Provides an estimate of logic and memory device resources that the Signal Tap Logic Analyzer configurations use.
No additional cost Intel® Quartus® Prime subscription and the Intel® Quartus® Prime Lite Edition include the Signal Tap Logic Analyzer.
Compatibility with other on-chip debugging utilities You can use the Signal Tap Logic Analyzer in tandem with any JTAG-based on-chip debugging tool, such as an In-System Memory Content editor, allowing you to change signal values in real-time while you are running an analysis with the Signal Tap Logic Analyzer.
Floating-Point Display Format To enable, click Edit > Bus Display Format > Floating-point


  • Single-precision floating-point format IEEE754 Single (32-bit).
  • Double-precision floating-point format IEEE754 Double (64-bit).