Intel® Quartus® Prime Standard Edition User Guide: Debug Tools

ID 683552
Date 9/24/2018
Document Table of Contents

5.1. The Signal Tap Logic Analyzer

The Signal Tap Logic Analyzer captures and displays real-time signal behavior in an FPGA design, allowing to examine the behavior of internal signals during normal device operation without the need for extra I/O pins or external lab equipment.

To facilitate the debugging process, you can save the captured data in device memory for later analysis. You can also filter data that is not relevant for debug by defining custom trigger-condition logic. The Signal Tap Logic Analyzer supports the highest number of channels, largest sample depth, and fastest clock speeds of any logic analyzer in the programmable logic market.

Figure 38.  Signal Tap Logic Analyzer Block Diagram

Note to figure:

  1. This diagram assumes that you compiled the Signal Tap Logic Analyzer with the design as a separate design partition using the Intel® Quartus® Prime incremental compilation feature. If you do not use incremental compilation, the Compiler integrates the Signal Tap logic with the design.

The Signal Tap Logic Analyzer is available as a stand-alone package or with a software subscription.

To take advantage of faster compile times when making changes to the Signal Tap Logic Analyzer, knowledge of the Intel® Quartus® Prime incremental compilation feature is helpful.

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