Intel® Quartus® Prime Standard Edition User Guide: Debug Tools

ID 683552
Date 9/24/2018
Document Table of Contents Creating a .stp File from a Design Instance

To generate a .stp file from parameterized HDL instances within your design:
  1. Open or create an Intel® Quartus® Prime project that includes one or more HDL instances of the Signal Tap logic analyzer.
  2. Click Processing > Start > Start Analysis & Synthesis.
  3. Click File > Create/Update > Create Signal Tap File from Design Instance(s).
  4. Specify a location for the .stp file that generates, and click Save.
    Figure 90.  Create Signal Tap File from Design Instances Dialog Box
    Note: If your project contains partial reconfiguration partitions, the Create Signal Tap File from Design Instance(s) dialog box displays a tree view of the PR partitions in the project. Select a partition from the view, and click Create Signal Tap file. The resultant .stp file that generates contains all HDL instances in the corresponding PR partition. The resultant .stp file does not include the instances in any nested partial reconfiguration partition.
    Figure 91. Selecting Partition for .stp File Generation

After successful .stp file creation, the Signal Tap Logic Analyzer appears. All the fields are read-only, except runtime-configurable trigger conditions.

Figure 92. Generated .stp File