1.1.2. Suggested Tools for Common Debugging Requirements
|Requirement||Signal Probe||Logic Analyzer Interface (LAI)||Signal Tap Logic Analyzer||Description|
|More Data Storage||N/A||X||—||
An external logic analyzer with the LAI tool allows you to store more captured data than the Signal Tap Logic Analyzer, because the external logic analyzer can provide access to a bigger buffer.
The Signal Probe tool does not capture or store data.
|Faster Debugging||X||X||—||You can use the LAI or the Signal Probe tool with external equipment, such as oscilloscopes and mixed signal oscilloscopes (MSOs). This ability provides access to timing mode, which allows you to debug combined streams of data.|
|Minimal Effect on Logic Design||X||X (2)||X (2)||The Signal Probe tool incrementally routes nodes to pins, with no effect on the design logic.
The LAI adds minimal logic to a design, requiring fewer device resources.
The Signal Tap Logic Analyzer has little effect on the design, because the Compiler considers the debug logic as a separate design partition.
|Short Compile and Recompile Time||X||X (2)||X (2)||
Signal Probe uses incremental routing to attach signals to previously reserved pins. This feature allows you to quickly recompile when you change the selection of source signals.
The Signal Tap Logic Analyzer and the LAI can refit their own design partitions to decrease recompilation time.
|Sophisticated Triggering Capability||N/A||N/A||X||The triggering capabilities of the Signal Tap Logic Analyzer are comparable to commercial logic analyzers.|
|Low I/O Usage||—||—||X||
The Signal Tap Logic Analyzer does not require additional output pins.
Both the LAI and Signal Probe require I/O pin assignments.
|Fast Data Acquisition||N/A||—||X||The Signal Tap Logic Analyzer can acquire data at speeds of over 200 MHz.
Signal integrity issues limit acquisition speed for external logic analyzers that use the LAI.
|No JTAG Connection Required||X||—||X||
Signal Probe and Signal Tap do not require a host for debugging purposes.
A FPGA design with the LAI requires an active JTAG connection to a host running the Intel® Quartus® Prime software.
|No External Equipment Required||—||—||X||
The Signal Tap Logic Analyzer only requires a JTAG connection from a host running the Intel® Quartus® Prime software or the stand-alone Signal Tap Logic Analyzer.
Signal Probe and the LAI require the use of external debugging equipment, such as multimeters, oscilloscopes, or logic analyzers.
Notes to Table:
Did you find the information on this page useful?