Intel® Quartus® Prime Standard Edition User Guide: Debug Tools

ID 683552
Date 9/24/2018
Document Table of Contents

8.2.2. In-System Sources and Probes IP Core Parameters

Use the template to instantiate the variation file in your design.
Table 70.  In-System Sources and Probes IP Port Information
Port Name Required? Direction Comments
probe[] No Input The outputs from your design.
source_clk No Input Source Data is written synchronously to this clock. This input is required if you turn on Source Clock in the Advanced Options box in the parameter editor.
source_ena No Input Clock enable signal for source_clk. This input is required if specified in the Advanced Options box in the parameter editor.
source[] No Output Used to drive inputs to user design.

You can include up to 128 instances of the in-system sources and probes IP core in your design, if your device has available resources. Each instance of the IP core uses a pair of registers per signal for the width of the widest port in the IP core. Additionally, there is some fixed overhead logic to accommodate communication between the IP core instances and the JTAG controller. You can also specify an additional pair of registers per source port for synchronization.

You can use the Intel® Quartus® Prime incremental compilation feature to reduce compilation time. Incremental compilation allows you to organize your design into logical partitions. During recompilation of a design, incremental compilation preserves the compilation results and performance of unchanged partitions and reduces design iteration time by compiling only modified design partitions.