Article ID: 000083300 Content Type: Troubleshooting Last Reviewed: 02/12/2014

Can I use REFCLK pin to generate reconfiguration clock (reconfig_clk) in Stratix IV GX/GT and Arria II GX devices?



No, you cannot use the REFCLK pin directly or indirectly to generate the reconfiguration clock (reconfig_clk), because a stable clock is required when ALTGX_RECONFIG block comes out of reset.  REFCLK clock may not be stable initially and could cause issues with offset cancellation process.

Following are a couple of recommendations:

1) Use a free running clock from a non transceiver IO clock pin that is stable at device power up.

2) You could use a GPLL to generate reconfig_clk sourced from an IO clock pin.   

Figure 1. Dynamic Reconfiguration reconfig_clk requirements

Figure x

Reconfig_reset should be asserted until GPLL clock output is stable. This can be accomplished by inserting an inverter between GPLL locked output and reconfig_reset input, as shown above. The reconfig_reset input is a synchronous reset, so inverted lock signal must be synchronized to the reconfig_clk clock domain. The locked status of GPLL may have glitch at the initial stage due to jittery input reference clock. A milliseconds filter should be implemented in this cases. 

Once the busy signal deasserts after initialization, re-asserting reconfig_reset does not restart the offset cancellation process.

To enable the reconfig_reset port to the alt_reconfig block, you need to enable “Channel and TX PLL select/reconfig” option and check off "Use \'reconfig_reset\' " option under Channel and TX PLL Reconfiguration tab.

Related Products

This article applies to 3 products

Arria® II FPGAs
Stratix® IV GX FPGA