Article ID: 000079312 Content Type: Troubleshooting Last Reviewed: 11/20/2013

When should reconfig_clk be stable after power up?

Environment

  • Stratix® IV GX FPGA
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Description

Reconfig_clk should be stable before reconfig_block controller starts Offset Cancellation process. There are two possible scenarios.

 

1. If input offset_cancellation_reset is not implemented, the reconfig_block controller starts the offset cancellation process right after FPGA is finished programming and switched to user mode (CONFIG_DONE=1). In PCIe® PIPE mode, reconfig_clk(50MHz) drives Reconfiguration Controller and the fixedclk(125MHz) drives the offset cancellation logic in the transceiver. Hence, both reconfig_clk and fixed_clk must be stable before CONFIG_DONE=1.

 

2. If input offset_cancellation_reset is implemented, the reconfig_block controller can be held in reset till the reconfig_clk is stable. The offset cancellation process is postponed until the offset_cancellation_reset is released. In PCIe PIPE mode, the fixedclk drives the transceiver reconfiguration logic. Hence, the reconfiguration controller should be in reset until both reconfig_clk and fixed_clk are stabled. 

    Note1: Because offset_cancellation process occurs only once when CONFIG_DONE event occurs, toggling the reset signals without reprogramming FPGA will not trigger it again.

     

    Note2: When offset_cacellation process is active, reconfiguration controller will assert "busy" signal. Therefore, in PCIe PIPE mode, reset logic must detect the first falling edge of "busy" signal before deasserting transceiver rx_analog_reset. 

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