Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 8/15/2024
Public
Document Table of Contents

12.4.3. Watchdog Reset Sequence

A watchdog timeout event triggers this reset sequence. Reset Manager asserts watchdog reset based on the watchdog timer register.
  1. Reset Manager does not perform L2FLUSH. Any content in the HPS L2 cache is lost after the reset. Any critical data should be stored in non-cached memory.
  2. Reset Manager performs the following handshakes:
    1. HMC handshaking, if enabled using the hdsken register.
    2. FPGA handshaking, if enabled using the hdsken register.
    3. ETR handshaking, if enabled using the hdsken register.
  3. Reset Manager initiates boot mode request handshake with Clock Manager.
  4. Reset Manager waits for an acknowledgement signal from Clock Manager, that indicates completion of the boot mode handshake before proceeding any further.
    • A cold reset request that occurs before the completion of this step takes precedence over the watchdog reset sequence.
    • A cold reset request that occurs after the completion of this step is delayed until the watchdog reset is completed.
  5. Reset Manager asserts Watchdog reset. After a definite time-period, Reset Manager de-asserts all modules in reset except MPU.
  6. Reset Manager waits until the ocramload.done bit is set.
  7. Reset Manager de-asserts L2/SCU using the coldmodrst.l2 register bit.
  8. Reset Manager de-asserts MPU cores using the mpumodrst.core[3:0] and coldmodrst.cpupor[3:0] register bits.
  9. You can de-assert peripheral modules using the per0modrst and per1modrst registers.