Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

ID 683686
Date 1/11/2022
Document Table of Contents
Give Feedback

5.1. Avalon-ST TX Interface

User application logic transfers data to the Transaction Layer of the PCIe IP core over the Avalon-ST TX interface.

Table 22.   Avalon-ST TX Datapath






Data for transmission. Transmit data bus. The Application Layer must provide a properly formatted TLP on the TX interface. The mapping of message TLPs is the same as the mapping of Transaction Layer TLPs with 4 dword headers. The number of data cycles must be correct for the length and address fields in the header. Issuing a packet with an incorrect number of data cycles results in the TX interface hanging and becoming unable to accept further requests.

Refer to the Qword Alignment figure in the Intel® Arria® 10 Avalon-ST Interface for PCIe Solutions User Guide for a detailed explanation of qword alignment on the Avalon-ST interface.

Data Alignment and Timing for 256-Bit Avalon-ST TX Interface in the Intel® Arria® 10 Avalon-ST Interface for PCIe Solutions User Guide for figures showing the mapping of the Transaction Layer’s TLP information to rx_st_data and examples of the timing of this interface.


Indicates first cycle of a TLP when asserted together with tx_st_valid.



Indicates last cycle of a TLP when asserted together with tx_st_valid.

tx_st_ready 3


Indicates that the SR-IOV Bridge is ready to accept data for transmission. The SRIOV Bridge deasserts this signal to throttle the data stream. tx_st_ready may be asserted during reset. The Application Layer should wait at least 2 clock cycles after the reset is released before issuing packets on the Avalon0ST TX interface. The Application Layer can monitor the reset_status signal to determine when the IP core has come out of reset.

If tx_st_ready is asserted by the Transaction Layer on cycle <n>, then <n + readyLatency> is a ready cycle, during which the Application Layer may assert valid and transfer data.

When tx_st_ready, tx_st_valid and tx_st_data are registered (the typical case), Intel recommends a readyLatency of 2 cycles to facilitate timing closure; however, a readyLatency of 1 cycle is possible. If no other delays are added to the read‑valid latency, the resulting delay corresponds to a readyLatency of 2.

tx_st_valid 3


Clocks tx_st_data to the core when tx_st_ready is also asserted. Between tx_st_sop and tx_st_eop, tx_st_valid must not be deasserted in the middle of a TLP except in response to tx_st_ready deassertion. When tx_st_ready deasserts, this signal must deassert within 1 or 2 clock cycles. When tx_st_ready reasserts, and tx_st_data is in mid-TLP, this signal must reassert within 2 cycles. The figure entitled 64-Bit Transaction Layer Backpressures the Application Layer illustrates the timing of this signal.

To facilitate timing closure, Intel recommends that you register both the tx_st_ready and tx_st_valid signals. If no other delays are added to the ready-valid latency, the resulting delay corresponds to a readyLatency of 2.



Indicates the number of qwords that are empty during cycles that contain the end of a packet. When asserted, the empty dwords are in the high-order bits. Valid only when tx_st_eop is asserted.

Indicates the number of upper words that contain data, resulting in the following encodings:
  • tx_st_empty=0: tx_st_data[255:0] contains valid data
  • tx_st_empty=1: tx_st_data[191:0] contains valid data
  • tx_st_empty=2: tx_st_data[127:0] contains valid data
  • tx_st_empty=3: tx_st_data[63:0]contains valid data


Indicates an error on transmitted TLP. This signal is used to nullify a packet. It should only be applied to posted and completion TLPs with payload. To nullify a packet, assert this signal for 1 cycle after the SOP and before the EOP. When a packet is nullified, the following packet should not be transmitted until the next clock cycle. tx_st_err is not available for packets that are 1 or 2 cycles long.

Note that tx_st_err must be asserted while the valid signal is asserted.



Byte parity is generated when you turn on Enable byte parity ports on Avalon ST interface on the System Settings tab of the parameter editor.Each bit represents odd parity of the associated byte of the tx_st_data bus. For example, bit[0] corresponds to tx_st_data[7:0], bit[1] corresponds to tx_st_data[15:8], and so on.
3 To be Avalon-ST compliant, your Application Layer must have a readyLatency of 1 or 2 cycles.