Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

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ID 683686
Date 1/11/2022
Public
Document Table of Contents

6.16.4. Initial VFs and Total VFs Registers

Table 79.  Initial VFs and Total VFs Registers - 0x20C

Bits

Description

Default Value

Access

[15:0]

Initial VFs. Specifies the initial number of VFs configured for this PF.

Same value as TotalVFs

RO

[31:16]

Total VFs. Specifies the total number of VFs attached to this PF.

Set in Platform Designer

RO
Table 80.  Function Dependency Link and NumVFs Registers - 0x210

Bit Location

Description

Default Value

Access

[15:0]

NumVFs. Specifies the number of VFs enabled for this PF. Writable only when the VF Enable bit in the SR-IOV Control Register is 0.

0

RW

[31:16]

Function Dependency Link

0

RO

Table 81.  VF Offset and Stride Registers - 0x214

Bits

Register Description

Default Value

Access

[15:0] VF Offset (offset of first VF’s Routing ID with respect to the Routing ID of its PF). In a system with 4 PFs, PF0 has a routing ID of 0, PF1 has a routing ID of 1, and so on. The following calculations determine the routing IDs for the VFs:
  • VF Offset for PF0 = TOTAL_PF_COUNT.
  • VF Offset for PF1 = (PF0_VF_COUNT + (TOTAL_PF1_COUNT -1))
  • VF Offset for PF2 = (PF0_VF_COUNT + PF1_VF_COUNT + (TOTAL_PF_COUNT – 2))
  • VF Offset for PF3 = (PF0_VF_COUNT + PF1_VF_COUNT + PF2_VF_COUNT + (TOTAL_PF_COUNT – 3))
Refer to description RO

[31:16]

VF Stride

1

RO

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