Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

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ID 683686
Date 1/11/2022
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3.2. Intel® Arria® 10 Avalon-ST Settings

Table 10.  System Settings for PCI Express

Parameter

Value

Description

Enable Avalon-ST reset output port On/Off

When On, the generated reset output port has the same functionality that the reset_status port included in the Reset and Link Status interface.

Enable byte parity ports on Avalon-ST interface

On/Off

When On, the RX and TX datapaths are parity protected. Parity is odd. The Application Layer must provide valid byte parity in the Avalon-ST TX direction.

This parameter is only available for the Avalon‑ST Intel® Arria® 10 Hard IP for PCI Express.

Enable multiple packets per cycle for the 256-bit interface

On/Off

When On, the 256‑bit Avalon‑ST interface supports the transmission of TLPs starting at any 128‑bit address boundary, allowing support for multiple packets in a single cycle. To support multiple packets per cycle, the Avalon‑ST interface includes 2 start of packet and end of packet signals for the 256‑bit Avalon‑ST interfaces. This is not supported for the Avalon-ST with SR-IOV interface.

Enable credit consumed selection port

On/Off

When you turn on this option, the core includes the tx_cons_cred_sel port. This parameter does not apply to the Avalon-MM interface.

Enable Configuration bypass (CfgBP)

On/Off

When On, the Intel® Arria® 10 Hard IP for PCI Express bypasses the Transaction Layer Configuration Space registers included as part of the Hard IP, allowing you to substitute a custom Configuration Space implemented in soft logic.

This parameter is not available for the Avalon‑MM IP Cores.

Enable local management interface (LMI)

On/Off

When On, your variant includes the optional LMI interface. This interface is used to log error descriptor information in the TLP header log registers. The LMI interface provides the same access to Configuration Space registers as Configuration TLP requests.

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